All boards are using the gen_atmel_mci driver now, so no need
to carry the old driver around.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
gen_atmel_mci works on AVR32 as well, so no need to use the legacy
mmc driver. This also has the nice side effect of being able to use
SDHC cards an those boards.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Align the card status polling with the Linux kernel and retry the
command at least five times. Also some cards apparently mishandle the
status bits, so make sure to check the card state too.
Signed-off-by: Jan Kloetzke <jan.kloetzke@dspg.com>
Cc: Andy Fleming <afleming@gmail.com>
A MMC/SD card may always go into the programming state (and hence be
busy) after a block write. Therefore always check the card state, even
after single block writes. On the other hand there is no need to check
the card status after a read.
Also make sure that errors during busy polling are propagated upwards.
Signed-off-by: Jan Kloetzke <jan.kloetzke@dspg.com>
Cc: Andy Fleming <afleming@gmail.com>
We are seeing occasional timeouts in the Tegra mmc code when
we are reading from external MMC cards. These don't seem to be
detrimental if they are handled properly. This CL properly
clears the "normal interrupt status register" (norintsts) in
error conditions. If we don't do this, when we come back into
mmc_send_cmd() the register will still contain status from the
last transaction.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Before we can send a command we need both the DATI (command inhibit on
mmc_dat line) bit and CMDI (command inhibit on mmc_cmd line) are clear.
The previous behavior of only checking on DATI was insufficient on some
cards and incorrect behavior in any case. This makes the code check
for both bits being clear and makes the error print more clear as
to what happened. DATI_CMDDIS is removed as it was unused elsewhere
in the code and stood for 'DATI is set, cmds are disabled still'.
Fix originally spotted by Peter Bigot.
Tested-by: Peter A. Bigot <bigotp@acm.org>
Tested-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-by: Andreas Müller <schnitzeltony@googlemail.com>
This patch modifies mxcmmc.c to be used
not only by i.MX27 but also by i.MX31 boards.
Both use the same SD controller, but have different
clock set-ups.
The i.MX27 imx_get_XXXclock functions are made static to
generic.c and a public mxc_get_clock() function
is provided. Pins, base address and prototypes for
an i.MX31 specific board_init_mmc() are provided.
Some of the i.MX27 clock getters are unused and marked
as such to avoid warnings (./MAKEALL -s mx27), but
the code was left in for future use.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
When the data cache is enabled we must flush on write and invalidate
on read. We also check that buffers are aligned to data cache lines
boundaries. With recent work in U-Boot this should generally be the case
but the warnings will catch problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The pointer to the registers used to control the Freescale ESDHC MMC
controller is not initialized correctly when using PIO mode. This is
fixed by initializing the pointer in the same way as all other sites
within the driver.
Examining the commit history shows that this was broken at introduction
due to a code change in upstream U-Boot to support the mx51 processor
family.
Reported-by: Jim Lentz <JLentz@zhone.com>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
On Tegra2, card-detection is implemented by passing the card-detection
GPIOs to the MMC driver at initialization time. Instead of implementing
the board_mmc_getcd() function, use the card-detect hook and allow
boards to override it by providing their own board_mmc_getcd()
implementation.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
This card-detect hook probably doesn't work. Perhaps somebody with more
knowledge about the hardware can comment on this. I think that perhaps
even the complete code from esdhc_init() could go into the getcd()
function instead or mmc_getcd() needs to be called at some later time
after mmc_init(), which, however, would require many other drivers to
change.
In addition to implementing the hook, this patch also removes the call
to the board_mmc_getcd() function which is now called from the MMC
framework and is no longer required here.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
Check for card detect each time an MMC/SD device is initialized. If card
detection is not implemented, this code behaves as before and continues
assuming a card is present. If no card is detected, has_init is reset
for the MMC/SD device (to force initialization next time) and an error
is returned.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
The new API no longer uses the extra cd parameter that was used to store
the card presence state. Instead, this information is returned via the
function's return value. board_mmc_getcd() returns -1 to indicate that
no card-detection mechanism is implemented; 0 indicates that no card is
present and 1 is returned if it was detected that a card is present.
The rationale for this change can be found in the following email
thread:
http://lists.denx.de/pipermail/u-boot/2011-November/110180.html
In summary, the old API was not consistent with the rest of the MMC API
which always passes a struct mmc as the first parameter. Furthermore the
cd parameter was used to mean "card absence" in some implementations and
"card presence" in others.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
Fix:
mv_sdhci.c: In function 'mv_sdh_init':
mv_sdhci.c:47:22: warning: the comparison will always
evaluate as 'true' for the address of 'mv_sdhci_writeb'
will never be NULL [-Waddress]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Lei Wen <leiwen@marvell.com>
This patch improve the performance by spliting flag examination code
in ftsdc010_send_cmd() into 3 functions.
This patch also reordered the function which made better capability to
some high performance cards against to the next version of ftsdc010
hardware.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Add a host capability checking to avoid the mmc stack
switch the card to HIGHSPEED mode when the card supports
HIGHSPEED while the host doesn't.
This patch avoid furthur transaction problem when the
mmc/sd card runs different mode to the host.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
The mmc host controller on the i.mx6q is called usdhc which
is redesigned based on the freescale esdhc controller.
The usdhc controller is almost compatible with esdhc except
it adds one mix register to support debug/SD3.0 and move
the low bit 0-6 of XFERTYP register to the mix control reg
low bit 0-6. Thus on i.mx6q, we have the following compared
with the previous soc: (can refer to RM of chapter 56.3.3)
i.mx6q:
mix control:
bit 31 - bit 7: Added for debug/SD3.0 support
bit 6 - bit 0: move in the XFERTYP register bit 6-0 on previous soc
XFERTYP register:
bit 31 - bit 7: the same as before,
bit 6 - bit 0: no-use
previous soc
mix control: no
XFERTYP register:
bit 31 - bit 0: xfertype information
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
tegra2_mmc_init() is implemented by the Tegra2 MMC driver. Since most of
the Tegra2-based boards will need to call it, this commit exports it in
the new public asm/arch/mmc.h header file to prevent each board from
providing its own prototype.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
GPIO configuration shall never be done inside a driver, never.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Pass the GPIO numbers for power and card detect to tegra2_mmc_init(), and
modify that function to perform all required GPIO initialization. This
removes the need for board files to perform these operations.
Move board_mmc_getcd() into tegra2_mmc.c now that the driver knows which
GPIOs to use.
Update affected call-sites in seaboard.c and harmony.c. Note that this
change should make all SD ports work on Harmony, since the required GPIO
setup is now being performed.
v4: Fix prototype of tegra2_mmc_init() in board.h to match driver change.
Remove prototype of gpio_config_mmc() from board.h
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cc: Andy Fleming <afleming@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This reverts commit 02f3029f18.
This patch add 3 times retry to CMD8 because the Marvell mmc controller
doesn't obey the power ramp up process in the SD specification 6.4.1.
(Please refer to figure 6.1 and 6.2 in the specification.)
The CMD0 should be send after power ramp up has been finished.
However, the Marvell mmc contorller must do power ramp up after the
first CMD0 command has been send.
This patch also affect existing platforms like Nokia N900 and other
platforms.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Acked-by: Lei Wen <leiwen@marvell.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
sdhci_readw does not work for host version read in Armada100 series
SoCs. This patch fix this issue by making a sdhci_readl call to get host
version.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Fix:
davinci_mmc.c: In function 'dmmc_wait_fifo_status':
davinci_mmc.c:72:7: warning: variable 'mmcstatus1' set but not used [-Wunused-but-set-variable]
davinci_mmc.c: In function 'dmmc_busy_wait':
davinci_mmc.c:89:7: warning: variable 'mmcstatus1' set but not used [-Wunused-but-set-variable]
Delete the unused variable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Fixing them here so that when the files are reused in
subsequent patches for omap5, avoids new checkpatch
warnings.
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This is a well encapsulated section of mmc_send_cmd, by moving
it to it's own function it increases the readability of mmc_send_cmd.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Currently when no expected completion condition occures in the
mmc_send_cmd while loop that is waiting for a data transfer to
complete the MMC driver just hangs.
This patch adds an arbitrary 2 second timeout. If nothing we
recognize occures within 2 seconds some diagnostic information
is printed and we fail out.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Currently if a DMA buffer straddles a buffer alignment boundary
(512KiB) then the DMA engine will pause and generate a DMA
interrupt. Since the DMA interrupt is not enabled it will hang
the MMC driver.
This patch adds support for restarting the DMA transfer. The
SYSTEM_ADDRESS register contains the next address that would have
been read/written when a boundary is hit. So we can read that
and write it back. The write triggers the resumption of the
transfer.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
This moves the magic numbers sprinkled about the MMC driver
to a single location in the header file and gives them
meaningful names.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Acked-by: Andy Fleming <afleming@gmail.com>
The new IO FPGA implementation for Versatile Express contains an MMCI
(PL180) cell with the FIFO extended to 128 words. This causes the
read_bytes() function to go into an infinite loop; as it will wait for
for the half-full signal (SDI_STA_RXFIFOBR) if there are more than 8
words remaining (SDI_FIFO_BURST_SIZE), but it won't receive this signal
once there are fewer than 64 words left to transfer.
One possible fix is to add some build time configuration to change
SDI_FIFO_BURST_SIZE for the new implementation. However, the problematic
code only seems to exist as a small performance optimisation, so the
solution implemented by this patch is to simply remove it. The error
checking following the loop is also removed as this will be handled by
code further down the function.
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Jon Medhurst <jon.medhurst@linaro.org>
This centralizes knowledge of MMC clocking into the MMC driver. This also
removes clock setup from the board files, which will simplify later changes
that modify the Harmony board to support the correct set of MMC controllers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cc: Andy Fleming <afleming@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
SDHCI spec need to reset the sdma base address while the software
try to accorss the 512k bytes address boundary. When meet such
accross behavior, sdhci controller would generate a interrupt
automatically, and software need handle this.
Signed-off-by: Lei Wen <leiwen@marvell.com>
As per JEDEC document JESD84-A441 (page 105) response for CMD7
(MMC_CMD_SELECT_CARD) response should be R1 instead of R1b. In uboot we
never take MMC to disconnected state and on powerup its always ideal
state which later goes to stand-by state.
from document footnote:
R1 while selecting from Stand-By State to Transfer State; R1b while
selecting from Disconnected State to Programming State.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
For we don't know mmc bus width from reading registers, the only way
to check is to test.
Current compare offset is:
EXT_CSD_PARTITIONING_SUPPORT
EXT_CSD_ERASE_GROUP_DEF
EXT_CSD_REV
EXT_CSD_HC_ERASE_GRP_SIZE
EXT_CSD_SEC_CNT
Signed-off-by: Lei Wen <leiwen@marvell.com>
Previous magic number is hard to parse its meaning, change it to
respective macro definition
Signed-off-by: Lei Wen <leiwen@marvell.com>
Acked-by: WOlfgang Denk <wd@denx.de>
Marvell 88SV331xV5 platform's sdhci host control is not very standard
with the spec in the 8bit handling. It need to set its private register
to switch to the 8bit mode which is not included in the standard sdhci
registers.
This patch mainly hacks the writeb method, and set its private register
if it find the driver is going to switch to the 8bit mode.
Signed-off-by: Lei Wen <leiwen@marvell.com>
For some controller it has dynamic clock gating, and only toggle out clk
when the first cmd0 send out, while some card strictly obey the 74
clocks rule, the interval may not be sufficient between the cmd0 and
this cmd8, retry to fulfil the clock requirement.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
pxa_mmc.c: In function 'mmc_cmd':
pxa_mmc.c:77:2: warning: format '%08x' expects type 'unsigned int', but argument
2 has type 'ulong'
pxa_mmc.c: In function 'mmc_block_read':
pxa_mmc.c:110:2: warning: format '%d' expects type 'int', but argument 4 has
type 'ulong'
pxa_mmc.c: In function 'pxa_mmc_write':
pxa_mmc.c:327:2: warning: format '%lx' expects type 'long unsigned int', but
argument 2 has type 'uchar *'
pxa_mmc.c:349:2: warning: format '%lx' expects type 'long unsigned int', but
argument 2 has type 'uchar *'
pxa_mmc.c:354:3: warning: format '%lx' expects type 'long unsigned int', but
argument 2 has type 'uchar *'
pxa_mmc.c:362:2: warning: format '%lx' expects type 'long unsigned int', but
argument 2 has type 'uchar *'
pxa_mmc.c:367:3: warning: format '%lx' expects type 'long unsigned int', but
argument 2 has type 'uchar *'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Not all omap families define OMAP_HSMMC[23]_BASE so condition those
cases in omap_mmc_init().
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This adds the required GPIO and pinmux configuration to make eMMC / SD work
on Seaboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This adds most of the clock functions required by board and driver code:
-query and adjust peripheral clocks
-query and adjust PLLs
-reset and enable control
These functions are plumbed in as required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Currently the mmc_change_freq and mmc_startup functions allocates
buffers on the stack that are passed down to the MMC device driver.
These buffers could be unaligned to the L1 dcache line size. This
causes problems when using DMA and with caches enabled.
This patch correctly cache alignes the buffers used for reading the
ext_csd data from an MMC device.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Currently the sd_change_freq function allocates two buffers on the
stack that it passes down to the MMC device driver. These buffers
could be unaligned to the L1 dcache line size. This causes problems
when using DMA and with caches enabled.
This patch correctly cache alignes the buffers used for reading the
scr register and switch status values from an MMC device.
Change-Id: Ifa8414f572ef907681bd2d5ff3950285a215357d
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Config VMMC voltage to 3V for MMC/SD card slot
and PBIAS settings needed for OMAP4
Fixes MMC/SD detection on boot from eMMC.
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Enable high capacity to host capability.
Fixes eMMC detection on boot from MMC/SD card.
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Sven Schnelle
Jan Kloetzke
Tom Warren
Tom Rini
Helmut Raiger
Simon Glass
Ira Snyder
Thierry Reding
Anatolij Gustschin
Macpaul Lin
Jason Liu
Marek Vasut
Stephen Warren
Ajay Bhargav
Heiko Schocher
Sricharan
Anton staaf
Jon Medhurst (Tixy)
Lei Wen
Tom Warren
Balaji T K