This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the following serdes/PHY setup code, the Armada-XP support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion. Hopefully other MVEBU SoC's will follow here.
Support for some SoC's has been removed in this version. This is:
MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused.
And its partial and not sufficient for this device in this stage.
So lets remove it to make the code clearer and increase the readability.
MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the
Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.
Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
is B0 and this is the only one that is actively supported in this code
version.
Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
on a custom fixed DDR configuration board (maxbcm).
Note:
This code has undergone many hours of coding-style cleanup and refactoring.
It still is not checkpatch clean though, I'm afraid. As the factoring of the
code has so many levels of indentation that many lines are longer than 80
chars. This might be some task to tackly later on.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This is used on the AXP boards, to pad u-boot.img to the desired offset in
SPI flash (only this boot target supported right now). This offset is
used by the SPL then to load u-boot.img into SDRAM and execute it there.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This build target now includes the SPL binary as the bin_hdr into the
kwb image. Its used on the AXP port with the mainlined DDR training code.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the db-mv784mp-gp eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
With this patchset the Marvell bin_hdr (DDR training) code is intergrated
into mainline U-Boot. We can remove the placeholder file again, which was
only introduced to make U-Boot compile and link again.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
This results in a much more readable callgraph, because now they
can't be confused with the function having exactly the same name
in the generic mmc code.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch allows to configure all the important DRAM parameters in Kconfig.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In addition to the current Android magic settings, allow to optionally use
DDR3 timing parameters, which are tailored for different clock frequencies
and JEDEC speed bins. This should improve reliability and performance.
Adding '+S:CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H=y' to the board defconfig
allows to use timings, which are calculated for the DDR3-1066F speed bin.
A lot of DDR3 chips, which are used in real Allwinner based devices,
support DDR3-1066F speed bin timings.
And adding '+S:CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y' should work
with any DDR3 chips, because this targets the slowest JEDEC speed bins.
The vendor magic values are still used by default for DRAM, but board
maintainers now have more flexibility in DRAM timings selection.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an
unstable image when active low v or hsync is used.
The problem seems to be specific to the OLinuxIno A13 (normal & micro)
boards. I've just looked up the schematics and they use an opendrain driver
for the vga sync lines, and with sync pulses it is the logical high->low
edge of the pulse which counts for the timing, which with an active low
sync is being driven by the pull-up, and that simply seems to not drive
it hard enough to get a stable image.
So force v and hsync active high on these boards. independent of what the
modeline says. This fixes the unstable image.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers;
it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro
USB socket for OTG and another for power in, HDMI, SATA, 5V power for
SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a
MIPI camera connector.
Like the BananaPi, this board needs GMAC_TX_DELAY set to 3 in order for
GMAC to work reliably at gigabit speeds.
For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano
Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
It turns out that the device_mode_data is rsb specific, rather then slave
specific, so integrate the rsb_set_device_mode() call into rsb_init().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
CONFIG_TARGET_FOO was only used in board/sunxi/Makefile to select the
dram config for sun5i and sun7i boards and in board/sunxi/gmac.c for some
special handling of the bananapi/bananapro (both sun7i), all sun5i and sun7i
boards have been moved over to using a single dram_sun5i_autoconfig file,
and the tx clk delay handling for the Banana boards now has its own Kconfig.
IOW nothing is using CONFIG_TARGET_FOO anymore, so remove it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
And use this to set the GMAC Transmit Clock Delay Chain value on Banana
boards, rather then keying of CONFIG_TARGET_FOO.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Currently we've separate detailed dram settings for all sun5i boards, this
moves them over to using auto dram configuration so that we can get rid of
all the per board dram_foo.c files.
This has been tested on a A10s-Olinuxino, A13-Olinuxino, A13-OlinuxinoM,
mk802-a10s and r7-tv-dongle board.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We do not need i2c support in the SPL when there is no PMIC (some sun4i
boards), or when the PMIC is not using i2c such as on sun6i and sun8i.
This reduces the SPL size from (e.g.) 21812 to 19260 bytes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add an explanation for how to set up git so that patman can find the alias
file. Fix up the get_maintainers message too.
Reported-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This brings in a additional small fix which was missed in a recent update
to the README.
Suggested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
True commit lines start at column zero. Anything that is indented
is part of the commit message instead. I noticed this by trying to
run buildman with commit e3a4facdfc
as master, which contained a reference to a Linux commit inside
the commit message. ProcessLine saw that as a genuite commit
line, and thus buildman tried to build it, and died with an
exception because that SHA is not present in the U-Boot tree.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
When run with the --dry-run argument patman prints out information
showing what it would do. This information currently doesn't line up
with what patman/git send-email really do. Some basic examples:
- If an email address is addressed via "Series-cc" and "Patch-cc" patman
shows that email address would be CC-ed two times.
- If an email address is addressed via "Series-to" and "Patch-cc" patman
shows that email address would be sent TO and CC-ed.
- If an email address is addressed from a combination of tag aliases,
get_maintainer.pl output, "Series-cc", "Patch-cc", etc patman shows
that the email address would be CC-ed multiple times.
Patman currently does try to send duplicate emails like the --dry-run
output shows, but "git send-email" intelligently removes duplicate
addresses so this patch shouldn't change the non-dry-run functionality.
Change patman's output and email addressing to line up with the
"git send-email" logic. This trims down patman's dry-run output and
prevents confusion about what patman will do when emails are actually
sent.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
It is painful to specify the full path to the device tree with the -d
option. It is normally kept in the same directory as U-Boot, so provide
an option to use this by default.
Signed-off-by: Simon Glass <sjg@chromium.org>
If for some reason DMA module fails to reset user oserves only this:
--->---
# dhcp
Trying dwmac.e0018000
FAIL
--->---
This message makes not much sense.
With proposed change error message will be more helpful:
--->---
# dhcp
Trying dwmac.e0018000
DMA reset timeout
FAIL
--->---
For example user may do power toggle to recover board functionality.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds a phy driver for the Micrel KSZ8895 switch. As the SoC MAC
is directly connected to the switch MAC the link to the switch is always up.
But the KSZ8895 switch can be hardwired in three configuration modes :
- not configurable with eventually an eeprom-stored configuration
- configurable by the mdio/mdc connection (SMI protocol)
- configurable by a SPI connection.
In not configurable mode, the switch starts automatically, but in the
other modes, it must be started programmatically, by writing 1 in
configuration register 1.
We only support the not configurable and mdio/mdc (aka SMI) modes here.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
If the PHY is not recognized don't access phydev (NULL)
and return 0 to signal failure.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
The Juno Development Platform is a physical Versatile Express
device with some differences from the emulated semihosting
models. The main difference is that the system is split in
a SoC and an FPGA where the SoC hosts the serial ports at
totally different adresses.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stefan Roese
DrEagle
Tom Rini
Siarhei Siamashka
Hans de Goede
Michal Suchanek
Paul Kocialkowski
Adam Sampson
Simon Glass
Scott Wood
Peter Tyser
Alexey Brodkin
Philippe De Muyter
Yoshinori Sato
Claudiu Manoil
Peng Fan
Michal Simek
Linus Walleij