/* * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_ARCH_MX7_IMX_REGS_H__ #define __ASM_ARCH_MX7_IMX_REGS_H__ #define ARCH_MXC #define ROM_SW_INFO_ADDR 0x000001E8 #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x00017FFF #define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00107FFF #define GIC400_ARB_BASE_ADDR 0x31000000 #define GIC400_ARB_END_ADDR 0x31007FFF #define APBH_DMA_ARB_BASE_ADDR 0x33000000 #define APBH_DMA_ARB_END_ADDR 0x33007FFF #define M4_BOOTROM_BASE_ADDR 0x00180000 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* GPV - PL301 configuration ports */ #define GPV0_BASE_ADDR 0x32000000 #define GPV1_BASE_ADDR 0x32100000 #define GPV2_BASE_ADDR 0x32200000 #define GPV3_BASE_ADDR 0x32300000 #define GPV4_BASE_ADDR 0x32400000 #define GPV5_BASE_ADDR 0x32500000 #define GPV6_BASE_ADDR 0x32600000 #define GPV7_BASE_ADDR 0x32700000 #define OCRAM_ARB_BASE_ADDR 0x00900000 #define OCRAM_ARB_END_ADDR 0x0091FFFF #define OCRAM_EPDC_BASE_ADDR 0x00920000 #define OCRAM_EPDC_END_ADDR 0x0093FFFF #define OCRAM_PXP_BASE_ADDR 0x00940000 #define OCRAM_PXP_END_ADDR 0x00947FFF #define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR #define IRAM_SIZE 0x00020000 #define AIPS1_ARB_BASE_ADDR 0x30000000 #define AIPS1_ARB_END_ADDR 0x303FFFFF #define AIPS2_ARB_BASE_ADDR 0x30400000 #define AIPS2_ARB_END_ADDR 0x307FFFFF #define AIPS3_ARB_BASE_ADDR 0x30800000 #define AIPS3_ARB_END_ADDR 0x30BFFFFF #define WEIM_ARB_BASE_ADDR 0x28000000 #define WEIM_ARB_END_ADDR 0x2FFFFFFF #define QSPI0_ARB_BASE_ADDR 0x60000000 #define QSPI0_ARB_END_ADDR 0x6FFFFFFF #define PCIE_ARB_BASE_ADDR 0x40000000 #define PCIE_ARB_END_ADDR 0x4FFFFFFF #define PCIE_REG_BASE_ADDR 0x33800000 #define PCIE_REG_END_ADDR 0x33803FFF #define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_END_ADDR 0xBFFFFFFF #define MMDC1_ARB_BASE_ADDR 0xC0000000 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF /* Cortex-A9 MPCore private memory region */ #define ARM_PERIPHBASE 0x31000000 #define SCU_BASE_ADDR ARM_PERIPHBASE #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) /* Defines for Blocks connected via AIPS (SkyBlue) */ #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR #define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR /* DAP base-address */ #define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR /* AIPS_TZ#1- On Platform */ #define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000) /* AIPS_TZ#1- Off Platform */ #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) #define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000) #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000) #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000) #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000) #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000) #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000) #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000) #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000) #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000) #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000) #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000) #define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000) #define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000) #define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000) #define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000) #define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000) #define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000) #define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000) #define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000) #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000) #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000) #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000) #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) #define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000) #define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000) #define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000) #define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000) /* AIPS_TZ#2- On Platform */ #define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000) /* AIPS_TZ#2- Off Platform */ #define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000) #define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000) #define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000) #define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000) #define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000) #define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000) #define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000) #define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000) #define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000) #define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000) #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000) #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000) #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) #define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) #define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) #define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000) #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000) #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000) /* AIPS_TZ#3 - Global enable (0) */ #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000) #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000) #define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000) #define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000) #define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000) #define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000) #define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000) #define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000) #define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000) #define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000) #define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000) /* AIPS_TZ#3- On Platform */ #define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000) /* AIPS_TZ#3- Off Platform */ #define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000) #define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR #define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000) #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) #define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000) #define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000) #define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000) #define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000) #define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000) #define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000) #define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000) #define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000) #define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000) #define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000) #define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000) #define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000) #define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000) #define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000) #define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000) #define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000) #define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) #define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) #define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) #define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) #define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000) #define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000) #define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000) #define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000) #define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000) #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR #define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR #define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR #define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 #define CONFIG_SYS_FSL_SEC_OFFSET 0 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ CONFIG_SYS_FSL_JR0_OFFSET) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include #include extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); /* System Reset Controller (SRC) */ struct src { u32 scr; u32 a7rcr0; u32 a7rcr1; u32 m4rcr; u32 reserved1; u32 ercr; u32 reserved2; u32 hsicphy_rcr; u32 usbophy1_rcr; u32 usbophy2_rcr; u32 mipiphy_rcr; u32 pciephy_rcr; u32 reserved3[10]; u32 sbmr1; u32 srsr; u32 reserved4[2]; u32 sisr; u32 simr; u32 sbmr2; u32 gpr1; u32 gpr2; u32 gpr3; u32 gpr4; u32 gpr5; u32 gpr6; u32 gpr7; u32 gpr8; u32 gpr9; u32 gpr10; u32 reserved5[985]; u32 ddrc_rcr; }; #define src_base ((struct src *)SRC_BASE_ADDR) #define SRC_M4_REG_OFFSET 0xC #define SRC_M4C_NON_SCLR_RST_OFFSET 0 #define SRC_M4C_NON_SCLR_RST_MASK BIT(0) #define SRC_M4_ENABLE_OFFSET 3 #define SRC_M4_ENABLE_MASK BIT(3) #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1) /* GPR0 Bit Fields */ #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7) #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7 /* GPR1 Bit Fields */ #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<