upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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153 lines
3.4 KiB
153 lines
3.4 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#ifndef _KWCPU_H
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#define _KWCPU_H
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#include <asm/system.h>
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#ifndef __ASSEMBLY__
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#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
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| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
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#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
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((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
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#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
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#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
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#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
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#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
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#define SYSRST_CNT_1SEC_VAL (25*1000000)
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#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
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enum memory_bank {
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BANK0,
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BANK1,
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BANK2,
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BANK3
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};
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enum kwcpu_winen {
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KWCPU_WIN_DISABLE,
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KWCPU_WIN_ENABLE
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};
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enum kwcpu_target {
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KWCPU_TARGET_RESERVED,
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KWCPU_TARGET_MEMORY,
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KWCPU_TARGET_1RESERVED,
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KWCPU_TARGET_SASRAM,
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KWCPU_TARGET_PCIE
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};
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enum kwcpu_attrib {
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KWCPU_ATTR_SASRAM = 0x01,
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KWCPU_ATTR_DRAM_CS0 = 0x0e,
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KWCPU_ATTR_DRAM_CS1 = 0x0d,
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KWCPU_ATTR_DRAM_CS2 = 0x0b,
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KWCPU_ATTR_DRAM_CS3 = 0x07,
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KWCPU_ATTR_NANDFLASH = 0x2f,
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KWCPU_ATTR_SPIFLASH = 0x1e,
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KWCPU_ATTR_BOOTROM = 0x1d,
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KWCPU_ATTR_PCIE_IO = 0xe0,
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KWCPU_ATTR_PCIE_MEM = 0xe8
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};
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/*
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* Default Device Address MAP BAR values
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*/
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#define KW_DEFADR_PCI_MEM 0x90000000
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#define KW_DEFADR_PCI_IO 0xC0000000
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#define KW_DEFADR_PCI_IO_REMAP 0xC0000000
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#define KW_DEFADR_SASRAM 0xC8010000
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#define KW_DEFADR_NANDF 0xD8000000
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#define KW_DEFADR_SPIF 0xE8000000
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#define KW_DEFADR_BOOTROM 0xF8000000
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/*
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* read feroceon/sheeva core extra feature register
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* using co-proc instruction
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*/
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static inline unsigned int readfr_extra_feature_reg(void)
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{
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unsigned int val;
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asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
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(val)::"cc");
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return val;
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}
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/*
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* write feroceon/sheeva core extra feature register
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* using co-proc instruction
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*/
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static inline void writefr_extra_feature_reg(unsigned int val)
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{
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asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
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(val):"cc");
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isb();
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}
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/*
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* MBus-L to Mbus Bridge Registers
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* Ref: Datasheet sec:A.3
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*/
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struct kwwin_registers {
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u32 ctrl;
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u32 base;
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u32 remap_lo;
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u32 remap_hi;
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};
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/*
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* CPU control and status Registers
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* Ref: Datasheet sec:A.3.2
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*/
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struct kwcpu_registers {
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u32 config; /*0x20100 */
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u32 ctrl_stat; /*0x20104 */
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u32 rstoutn_mask; /* 0x20108 */
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u32 sys_soft_rst; /* 0x2010C */
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u32 ahb_mbus_cause_irq; /* 0x20110 */
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u32 ahb_mbus_mask_irq; /* 0x20114 */
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u32 pad1[2];
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u32 ftdll_config; /* 0x20120 */
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u32 pad2;
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u32 l2_cfg; /* 0x20128 */
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};
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/*
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* GPIO Registers
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* Ref: Datasheet sec:A.19
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*/
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struct kwgpio_registers {
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u32 dout;
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u32 oe;
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u32 blink_en;
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u32 din_pol;
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u32 din;
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u32 irq_cause;
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u32 irq_mask;
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u32 irq_level;
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};
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/*
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* functions
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*/
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unsigned int mvebu_sdram_bar(enum memory_bank bank);
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unsigned int mvebu_sdram_bs(enum memory_bank bank);
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void mvebu_sdram_size_adjust(enum memory_bank bank);
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int kw_config_adr_windows(void);
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void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
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unsigned int gpp0_oe, unsigned int gpp1_oe);
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int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
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unsigned int mpp16_23, unsigned int mpp24_31,
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unsigned int mpp32_39, unsigned int mpp40_47,
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unsigned int mpp48_55);
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unsigned int kw_winctrl_calcsize(unsigned int sizeval);
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#endif /* __ASSEMBLY__ */
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#endif /* _KWCPU_H */
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