upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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766 lines
19 KiB
766 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Google, Inc
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/arch/cru_rk3036.h>
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#include <asm/arch/grf_rk3036.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sdram_rk3036.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/uart.h>
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/*
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* we can not fit the code to access the device tree in SPL
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* (due to 4K SRAM size limits), so these are hard-coded
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*/
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#define CRU_BASE 0x20000000
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#define GRF_BASE 0x20008000
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#define DDR_PHY_BASE 0x2000a000
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#define DDR_PCTL_BASE 0x20004000
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#define CPU_AXI_BUS_BASE 0x10128000
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struct rk3036_sdram_priv {
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struct rk3036_cru *cru;
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struct rk3036_grf *grf;
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struct rk3036_ddr_phy *phy;
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struct rk3036_ddr_pctl *pctl;
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struct rk3036_service_sys *axi_bus;
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/* ddr die config */
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struct rk3036_ddr_config ddr_config;
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};
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/*
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* use integer mode, dpll output 792MHz and ddr get 396MHz
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* refdiv, fbdiv, postdiv1, postdiv2
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*/
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const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
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/* 396Mhz ddr timing */
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const struct rk3036_ddr_timing ddr_timing = {0x18c,
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{0x18c, 0xc8, 0x1f4, 0x27, 0x4e,
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0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04,
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0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03,
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0x0c, 0x28, 0x100, 0x0, 0x04, 0x0},
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{{0x420, 0x42, 0x0, 0x0}, 0x01, 0x60},
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{0x24717315} };
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/*
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* [7:6] bank(n:n bit bank)
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* [5:4] row(13+n)
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* [3] cs(0:1 cs, 1:2 cs)
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* [2:1] bank(n:n bit bank)
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* [0] col(10+n)
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*/
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const char ddr_cfg_2_rbc[] = {
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((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 1),
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((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 0),
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((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 0),
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((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 0),
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((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 1),
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((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 1),
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((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 1),
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((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 0),
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((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 1),
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((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 0),
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((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 1),
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((1 << 6) | (2 << 4) | (0 << 3) | (2 << 1) | 0),
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((3 << 6) | (2 << 4) | (0 << 3) | (0 << 1) | 1),
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((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 0),
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};
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/* DDRPHY REG */
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enum {
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/* DDRPHY_REG1 */
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SOFT_RESET_MASK = 3,
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SOFT_RESET_SHIFT = 2,
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/* DDRPHY_REG2 */
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MEMORY_SELECT_DDR3 = 0 << 6,
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DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
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DQS_SQU_CAL_START = 1 << 0,
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DQS_SQU_NO_CAL = 0 << 0,
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/* DDRPHY_REG2A */
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CMD_DLL_BYPASS = 1 << 4,
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CMD_DLL_BYPASS_DISABLE = 0 << 4,
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HIGH_8BIT_DLL_BYPASS = 1 << 3,
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HIGH_8BIT_DLL_BYPASS_DISABLE = 0 << 3,
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LOW_8BIT_DLL_BYPASS = 1 << 2,
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LOW_8BIT_DLL_BYPASS_DISABLE = 0 << 2,
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/* DDRPHY_REG19 */
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CMD_FEEDBACK_ENABLE = 1 << 5,
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CMD_SLAVE_DLL_INVERSE_MODE = 1 << 4,
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CMD_SLAVE_DLL_NO_INVERSE_MODE = 0 << 4,
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CMD_SLAVE_DLL_ENALBE = 1 << 3,
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CMD_TX_SLAVE_DLL_DELAY_MASK = 7,
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CMD_TX_SLAVE_DLL_DELAY_SHIFT = 0,
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/* DDRPHY_REG6 */
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LEFT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4,
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LEFT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4,
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LEFT_CHN_TX_DQ_DLL_ENABLE = 1 << 3,
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LEFT_CHN_TX_DQ_DLL_DELAY_MASK = 7,
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LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0,
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/* DDRPHY_REG8 */
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LEFT_CHN_RX_DQS_DELAY_TAP_MASK = 3,
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LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0,
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/* DDRPHY_REG9 */
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RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4,
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RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4,
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RIGHT_CHN_TX_DQ_DLL_ENABLE = 1 << 3,
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RIGHT_CHN_TX_DQ_DLL_DELAY_MASK = 7,
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RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0,
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/* DDRPHY_REG11 */
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RIGHT_CHN_RX_DQS_DELAY_TAP_MASK = 3,
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RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0,
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/* DDRPHY_REG62 */
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CAL_DONE_MASK = 3,
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HIGH_8BIT_CAL_DONE = 1 << 1,
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LOW_8BIT_CAL_DONE = 1 << 0,
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};
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/* PTCL */
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enum {
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/* PCTL_DFISTCFG0 */
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DFI_INIT_START = 1 << 0,
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DFI_DATA_BYTE_DISABLE_EN = 1 << 2,
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/* PCTL_DFISTCFG1 */
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DFI_DRAM_CLK_SR_EN = 1 << 0,
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DFI_DRAM_CLK_DPD_EN = 1 << 1,
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/* PCTL_DFISTCFG2 */
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DFI_PARITY_INTR_EN = 1 << 0,
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DFI_PARITY_EN = 1 << 1,
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/* PCTL_DFILPCFG0 */
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TLP_RESP_TIME_SHIFT = 16,
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LP_SR_EN = 1 << 8,
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LP_PD_EN = 1 << 0,
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/* PCTL_DFIODTCFG */
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RANK0_ODT_WRITE_SEL = 1 << 3,
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RANK1_ODT_WRITE_SEL = 1 << 11,
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/* PCTL_DFIODTCFG1 */
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ODT_LEN_BL8_W_SHIFT = 16,
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/* PCTL_MCFG */
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TFAW_CFG_MASK = 3,
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TFAW_CFG_SHIFT = 18,
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PD_EXIT_SLOW_MODE = 0 << 17,
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PD_ACTIVE_POWER_DOWN = 1 << 16,
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PD_IDLE_MASK = 0xff,
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PD_IDLE_SHIFT = 8,
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MEM_BL4 = 0 << 0,
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MEM_BL8 = 1 << 0,
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/* PCTL_MCFG1 */
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HW_EXIT_IDLE_EN_MASK = 1,
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HW_EXIT_IDLE_EN_SHIFT = 31,
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SR_IDLE_MASK = 0x1ff,
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SR_IDLE_SHIFT = 0,
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/* PCTL_SCFG */
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HW_LOW_POWER_EN = 1 << 0,
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/* PCTL_POWCTL */
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POWER_UP_START = 1 << 0,
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/* PCTL_POWSTAT */
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POWER_UP_DONE = 1 << 0,
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/* PCTL_MCMD */
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START_CMD = 1 << 31,
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BANK_ADDR_MASK = 7,
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BANK_ADDR_SHIFT = 17,
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CMD_ADDR_MASK = 0x1fff,
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CMD_ADDR_SHIFT = 4,
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DESELECT_CMD = 0,
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PREA_CMD,
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REF_CMD,
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MRS_CMD,
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ZQCS_CMD,
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ZQCL_CMD,
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RSTL_CMD,
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MRR_CMD = 8,
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/* PCTL_STAT */
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INIT_MEM = 0,
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CONFIG,
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CONFIG_REQ,
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ACCESS,
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ACCESS_REQ,
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LOW_POWER,
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LOW_POWER_ENTRY_REQ,
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LOW_POWER_EXIT_REQ,
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PCTL_STAT_MASK = 7,
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/* PCTL_SCTL */
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INIT_STATE = 0,
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CFG_STATE = 1,
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GO_STATE = 2,
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SLEEP_STATE = 3,
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WAKEUP_STATE = 4,
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};
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/* GRF_SOC_CON2 */
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#define MSCH4_MAINDDR3 (1 << 7)
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#define PHY_DRV_ODT_SET(n) ((n << 4) | n)
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#define DDR3_DLL_RESET (1 << 8)
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/* CK pull up/down driver strength control */
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enum {
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PHY_RON_DISABLE = 0,
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PHY_RON_309OHM = 1,
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PHY_RON_155OHM,
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PHY_RON_103OHM = 3,
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PHY_RON_63OHM = 5,
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PHY_RON_45OHM = 7,
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PHY_RON_77OHM,
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PHY_RON_62OHM,
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PHY_RON_52OHM,
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PHY_RON_44OHM,
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PHY_RON_39OHM,
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PHY_RON_34OHM,
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PHY_RON_31OHM,
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PHY_RON_28OHM,
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};
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/* DQ pull up/down control */
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enum {
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PHY_RTT_DISABLE = 0,
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PHY_RTT_861OHM = 1,
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PHY_RTT_431OHM,
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PHY_RTT_287OHM,
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PHY_RTT_216OHM,
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PHY_RTT_172OHM,
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PHY_RTT_145OHM,
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PHY_RTT_124OHM,
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PHY_RTT_215OHM,
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PHY_RTT_144OHM = 0xa,
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PHY_RTT_123OHM,
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PHY_RTT_108OHM,
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PHY_RTT_96OHM,
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PHY_RTT_86OHM,
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PHY_RTT_78OHM,
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};
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/* DQS squelch DLL delay */
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enum {
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DQS_DLL_NO_DELAY = 0,
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DQS_DLL_22P5_DELAY,
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DQS_DLL_45_DELAY,
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DQS_DLL_67P5_DELAY,
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DQS_DLL_90_DELAY,
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DQS_DLL_112P5_DELAY,
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DQS_DLL_135_DELAY,
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DQS_DLL_157P5_DELAY,
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};
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/* GRF_OS_REG1 */
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enum {
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/*
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* 000: lpddr
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* 001: ddr
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* 010: ddr2
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* 011: ddr3
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* 100: lpddr2-s2
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* 101: lpddr2-s4
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* 110: lpddr3
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*/
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DDR_TYPE_MASK = 7,
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DDR_TYPE_SHIFT = 13,
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/* 0: 1 chn, 1: 2 chn */
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DDR_CHN_CNT_SHIFT = 12,
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/* 0: 1 rank, 1: 2 rank */
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DDR_RANK_CNT_MASK = 1,
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DDR_RANK_CNT_SHIFT = 11,
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/*
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* 00: 9col
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* 01: 10col
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* 10: 11col
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* 11: 12col
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*/
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DDR_COL_MASK = 3,
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DDR_COL_SHIFT = 9,
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/* 0: 8 bank, 1: 4 bank*/
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DDR_BANK_MASK = 1,
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DDR_BANK_SHIFT = 8,
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/*
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* 00: 13 row
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* 01: 14 row
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* 10: 15 row
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* 11: 16 row
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*/
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DDR_CS0_ROW_MASK = 3,
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DDR_CS0_ROW_SHIFT = 6,
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DDR_CS1_ROW_MASK = 3,
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DDR_CS1_ROW_SHIFT = 4,
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/*
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* 00: 32 bit
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* 01: 16 bit
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* 10: 8 bit
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* rk3036 only support 16bit
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*/
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DDR_BW_MASK = 3,
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DDR_BW_SHIFT = 2,
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DDR_DIE_BW_MASK = 3,
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DDR_DIE_BW_SHIFT = 0,
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};
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static void rkdclk_init(struct rk3036_sdram_priv *priv)
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{
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struct rk3036_pll *pll = &priv->cru->pll[1];
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/* pll enter slow-mode */
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rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
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DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
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/* use integer mode */
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rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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rk_clrsetreg(&pll->con0,
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PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
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(dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
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dpll_init_cfg.fbdiv);
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rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
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(dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
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dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
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/* waiting for pll lock */
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while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
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rockchip_udelay(1);
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/* PLL enter normal-mode */
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rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
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DPLL_MODE_NORM << DPLL_MODE_SHIFT);
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}
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static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
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{
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int i;
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for (i = 0; i < n / sizeof(u32); i++) {
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writel(*src, dest);
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src++;
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dest++;
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}
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}
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void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
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{
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struct rk3036_ddr_phy *ddr_phy = priv->phy;
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rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
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1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT |
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1 << DDRPHY_SRST_SHIFT,
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1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
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1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
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rockchip_udelay(10);
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rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
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1 << DDRPHY_SRST_SHIFT);
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rockchip_udelay(10);
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rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
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1 << DDRCTRL_SRST_SHIFT);
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rockchip_udelay(10);
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clrsetbits_le32(&ddr_phy->ddrphy_reg1,
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SOFT_RESET_MASK << SOFT_RESET_SHIFT,
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0 << SOFT_RESET_SHIFT);
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rockchip_udelay(10);
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clrsetbits_le32(&ddr_phy->ddrphy_reg1,
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SOFT_RESET_MASK << SOFT_RESET_SHIFT,
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3 << SOFT_RESET_SHIFT);
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rockchip_udelay(1);
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}
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void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
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{
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struct rk3036_ddr_phy *ddr_phy = priv->phy;
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if (freq < ddr_timing.freq) {
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writel(CMD_DLL_BYPASS | HIGH_8BIT_DLL_BYPASS |
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LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a);
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writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_90 |
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LEFT_CHN_TX_DQ_DLL_ENABLE |
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(0 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) <<
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LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6);
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writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 |
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RIGHT_CHN_TX_DQ_DLL_ENABLE |
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(0 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) <<
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RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT,
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&ddr_phy->ddrphy_reg9);
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} else {
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writel(CMD_DLL_BYPASS_DISABLE | HIGH_8BIT_DLL_BYPASS_DISABLE |
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LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a);
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writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_0 |
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LEFT_CHN_TX_DQ_DLL_ENABLE |
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(4 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) <<
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LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT,
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&ddr_phy->ddrphy_reg6);
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writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 |
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RIGHT_CHN_TX_DQ_DLL_ENABLE |
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(4 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) <<
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RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT,
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&ddr_phy->ddrphy_reg9);
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}
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writel(CMD_SLAVE_DLL_NO_INVERSE_MODE | CMD_SLAVE_DLL_ENALBE |
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(0 & CMD_TX_SLAVE_DLL_DELAY_MASK) <<
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CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19);
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/* 45 degree delay */
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writel((DQS_DLL_45_DELAY & LEFT_CHN_RX_DQS_DELAY_TAP_MASK) <<
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LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8);
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writel((DQS_DLL_45_DELAY & RIGHT_CHN_RX_DQS_DELAY_TAP_MASK) <<
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RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11);
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}
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static void send_command(struct rk3036_ddr_pctl *pctl,
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u32 rank, u32 cmd, u32 arg)
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|
{
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writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
|
|
rockchip_udelay(1);
|
|
while (readl(&pctl->mcmd) & START_CMD)
|
|
;
|
|
}
|
|
|
|
static void memory_init(struct rk3036_sdram_priv *priv)
|
|
{
|
|
struct rk3036_ddr_pctl *pctl = priv->pctl;
|
|
|
|
send_command(pctl, 3, DESELECT_CMD, 0);
|
|
rockchip_udelay(1);
|
|
send_command(pctl, 3, PREA_CMD, 0);
|
|
send_command(pctl, 3, MRS_CMD,
|
|
(0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
|
|
(ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) <<
|
|
CMD_ADDR_SHIFT);
|
|
|
|
send_command(pctl, 3, MRS_CMD,
|
|
(0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
|
|
(ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) <<
|
|
CMD_ADDR_SHIFT);
|
|
|
|
send_command(pctl, 3, MRS_CMD,
|
|
(0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
|
|
(ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) <<
|
|
CMD_ADDR_SHIFT);
|
|
|
|
send_command(pctl, 3, MRS_CMD,
|
|
(0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
|
|
(ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) <<
|
|
CMD_ADDR_SHIFT | DDR3_DLL_RESET);
|
|
|
|
send_command(pctl, 3, ZQCL_CMD, 0);
|
|
}
|
|
|
|
static void data_training(struct rk3036_sdram_priv *priv)
|
|
{
|
|
struct rk3036_ddr_phy *ddr_phy = priv->phy;
|
|
struct rk3036_ddr_pctl *pctl = priv->pctl;
|
|
u32 value;
|
|
|
|
/* disable auto refresh */
|
|
value = readl(&pctl->trefi),
|
|
writel(0, &pctl->trefi);
|
|
|
|
clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
|
|
DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
|
|
|
|
rockchip_udelay(1);
|
|
while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
|
|
(HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
|
|
;
|
|
}
|
|
|
|
clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
|
|
DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_NO_CAL);
|
|
|
|
/*
|
|
* since data training will take about 20us, so send some auto
|
|
* refresh(about 7.8us) to complement the lost time
|
|
*/
|
|
send_command(pctl, 3, REF_CMD, 0);
|
|
send_command(pctl, 3, REF_CMD, 0);
|
|
send_command(pctl, 3, REF_CMD, 0);
|
|
|
|
writel(value, &pctl->trefi);
|
|
}
|
|
|
|
static void move_to_config_state(struct rk3036_sdram_priv *priv)
|
|
{
|
|
unsigned int state;
|
|
struct rk3036_ddr_pctl *pctl = priv->pctl;
|
|
|
|
while (1) {
|
|
state = readl(&pctl->stat) & PCTL_STAT_MASK;
|
|
switch (state) {
|
|
case LOW_POWER:
|
|
writel(WAKEUP_STATE, &pctl->sctl);
|
|
while ((readl(&pctl->stat) & PCTL_STAT_MASK)
|
|
!= ACCESS)
|
|
;
|
|
/*
|
|
* If at low power state, need wakeup first, and then
|
|
* enter the config, so fallthrough
|
|
*/
|
|
case ACCESS:
|
|
/* fallthrough */
|
|
case INIT_MEM:
|
|
writel(CFG_STATE, &pctl->sctl);
|
|
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
|
|
;
|
|
break;
|
|
case CONFIG:
|
|
return;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void move_to_access_state(struct rk3036_sdram_priv *priv)
|
|
{
|
|
unsigned int state;
|
|
struct rk3036_ddr_pctl *pctl = priv->pctl;
|
|
|
|
while (1) {
|
|
state = readl(&pctl->stat) & PCTL_STAT_MASK;
|
|
switch (state) {
|
|
case LOW_POWER:
|
|
writel(WAKEUP_STATE, &pctl->sctl);
|
|
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
|
|
;
|
|
break;
|
|
case INIT_MEM:
|
|
writel(CFG_STATE, &pctl->sctl);
|
|
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
|
|
;
|
|
/* fallthrough */
|
|
case CONFIG:
|
|
writel(GO_STATE, &pctl->sctl);
|
|
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
|
|
;
|
|
break;
|
|
case ACCESS:
|
|
return;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void pctl_cfg(struct rk3036_sdram_priv *priv)
|
|
{
|
|
struct rk3036_ddr_pctl *pctl = priv->pctl;
|
|
u32 burst_len;
|
|
u32 reg;
|
|
|
|
writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
|
|
writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1);
|
|
writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
|
|
writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
|
|
&pctl->dfilpcfg0);
|
|
|
|
writel(1, &pctl->dfitphyupdtype0);
|
|
writel(0x0d, &pctl->dfitphyrdlat);
|
|
|
|
/* cs0 and cs1 write odt enable */
|
|
writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
|
|
&pctl->dfiodtcfg);
|
|
|
|
/* odt write length */
|
|
writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
|
|
|
|
/* phyupd and ctrlupd disabled */
|
|
writel(0, &pctl->dfiupdcfg);
|
|
|
|
if ((ddr_timing.noc_timing.burstlen << 1) == 4)
|
|
burst_len = MEM_BL4;
|
|
else
|
|
burst_len = MEM_BL8;
|
|
|
|
copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u,
|
|
sizeof(struct rk3036_pctl_timing));
|
|
reg = readl(&pctl->tcl);
|
|
writel(reg - 3, &pctl->dfitrddataen);
|
|
reg = readl(&pctl->tcwl);
|
|
writel(reg - 1, &pctl->dfitphywrlat);
|
|
|
|
writel(burst_len | (1 & TFAW_CFG_MASK) << TFAW_CFG_SHIFT |
|
|
PD_EXIT_SLOW_MODE | PD_ACTIVE_POWER_DOWN |
|
|
(0 & PD_IDLE_MASK) << PD_IDLE_SHIFT,
|
|
&pctl->mcfg);
|
|
|
|
writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2);
|
|
setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
|
|
}
|
|
|
|
static void phy_cfg(struct rk3036_sdram_priv *priv)
|
|
{
|
|
struct rk3036_ddr_phy *ddr_phy = priv->phy;
|
|
struct rk3036_service_sys *axi_bus = priv->axi_bus;
|
|
|
|
writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming);
|
|
writel(0x3f, &axi_bus->readlatency);
|
|
|
|
writel(MEMORY_SELECT_DDR3 | DQS_SQU_CAL_NORMAL_MODE,
|
|
&ddr_phy->ddrphy_reg2);
|
|
|
|
clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl);
|
|
writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a);
|
|
writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16);
|
|
writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22);
|
|
writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25);
|
|
writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26);
|
|
writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27);
|
|
writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28);
|
|
}
|
|
|
|
void dram_cfg_rbc(struct rk3036_sdram_priv *priv)
|
|
{
|
|
char noc_config;
|
|
int i = 0;
|
|
struct rk3036_ddr_config config = priv->ddr_config;
|
|
struct rk3036_service_sys *axi_bus = priv->axi_bus;
|
|
|
|
move_to_config_state(priv);
|
|
|
|
/* 2bit in BIT1, 2 */
|
|
if (config.rank == 2) {
|
|
noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 |
|
|
1 << 3 | (config.col - 10);
|
|
if (noc_config == ddr_cfg_2_rbc[9]) {
|
|
i = 9;
|
|
goto finish;
|
|
} else if (noc_config == ddr_cfg_2_rbc[10]) {
|
|
i = 10;
|
|
goto finish;
|
|
}
|
|
}
|
|
|
|
noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 |
|
|
(config.col - 10);
|
|
|
|
for (i = 0; i < sizeof(ddr_cfg_2_rbc); i++) {
|
|
if (noc_config == ddr_cfg_2_rbc[i])
|
|
goto finish;
|
|
}
|
|
|
|
/* bank: 1 bit in BIT6,7, 1bit in BIT1, 2 */
|
|
noc_config = 1 << 6 | (config.cs0_row - 13) << 4 |
|
|
2 << 1 | (config.col - 10);
|
|
if (noc_config == ddr_cfg_2_rbc[11]) {
|
|
i = 11;
|
|
goto finish;
|
|
}
|
|
|
|
/* bank: 2bit in BIT6,7 */
|
|
noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 |
|
|
(config.col - 10);
|
|
|
|
if (noc_config == ddr_cfg_2_rbc[0])
|
|
i = 0;
|
|
else if (noc_config == ddr_cfg_2_rbc[12])
|
|
i = 12;
|
|
else if (noc_config == ddr_cfg_2_rbc[13])
|
|
i = 13;
|
|
finish:
|
|
writel(i, &axi_bus->ddrconf);
|
|
move_to_access_state(priv);
|
|
}
|
|
|
|
static void sdram_all_config(struct rk3036_sdram_priv *priv)
|
|
{
|
|
u32 os_reg = 0;
|
|
u32 cs1_row = 0;
|
|
struct rk3036_ddr_config config = priv->ddr_config;
|
|
|
|
if (config.rank > 1)
|
|
cs1_row = config.cs1_row - 13;
|
|
|
|
os_reg = config.ddr_type << DDR_TYPE_SHIFT |
|
|
0 << DDR_CHN_CNT_SHIFT |
|
|
(config.rank - 1) << DDR_RANK_CNT_SHIFT |
|
|
(config.col - 9) << DDR_COL_SHIFT |
|
|
(config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
|
|
(config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
|
|
cs1_row << DDR_CS1_ROW_SHIFT |
|
|
1 << DDR_BW_SHIFT |
|
|
(2 >> config.bw) << DDR_DIE_BW_SHIFT;
|
|
writel(os_reg, &priv->grf->os_reg[1]);
|
|
}
|
|
|
|
size_t sdram_size(void)
|
|
{
|
|
u32 size, os_reg, cs0_row, cs1_row, col, bank, rank;
|
|
struct rk3036_grf *grf = (void *)GRF_BASE;
|
|
|
|
os_reg = readl(&grf->os_reg[1]);
|
|
|
|
cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK);
|
|
cs1_row = 13 + ((os_reg >> DDR_CS1_ROW_SHIFT) & DDR_CS1_ROW_MASK);
|
|
col = 9 + ((os_reg >> DDR_COL_SHIFT) & DDR_COL_MASK);
|
|
bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK);
|
|
rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK);
|
|
|
|
/* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */
|
|
size = 1 << (cs0_row + col + bank + 1);
|
|
|
|
if (rank > 1)
|
|
size += size >> (cs0_row - cs1_row);
|
|
|
|
return size;
|
|
}
|
|
|
|
void sdram_init(void)
|
|
{
|
|
struct rk3036_sdram_priv sdram_priv;
|
|
|
|
sdram_priv.cru = (void *)CRU_BASE;
|
|
sdram_priv.grf = (void *)GRF_BASE;
|
|
sdram_priv.phy = (void *)DDR_PHY_BASE;
|
|
sdram_priv.pctl = (void *)DDR_PCTL_BASE;
|
|
sdram_priv.axi_bus = (void *)CPU_AXI_BUS_BASE;
|
|
|
|
get_ddr_config(&sdram_priv.ddr_config);
|
|
sdram_all_config(&sdram_priv);
|
|
rkdclk_init(&sdram_priv);
|
|
phy_pctrl_reset(&sdram_priv);
|
|
phy_dll_bypass_set(&sdram_priv, ddr_timing.freq);
|
|
pctl_cfg(&sdram_priv);
|
|
phy_cfg(&sdram_priv);
|
|
writel(POWER_UP_START, &sdram_priv.pctl->powctl);
|
|
while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE))
|
|
;
|
|
memory_init(&sdram_priv);
|
|
move_to_config_state(&sdram_priv);
|
|
data_training(&sdram_priv);
|
|
move_to_access_state(&sdram_priv);
|
|
dram_cfg_rbc(&sdram_priv);
|
|
}
|
|
|