upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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47 lines
1.1 KiB
47 lines
1.1 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Keystone2: DDR3 initialization
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*
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* (C) Copyright 2014-2015
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <common.h>
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#include "ddr3_cfg.h"
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#include <asm/arch/ddr3.h>
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static struct pll_init_data ddr3_400 = DDR3_PLL_400;
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static struct pll_init_data ddr3_333 = DDR3_PLL_333;
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u32 ddr3_init(void)
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{
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struct ddr3_spd_cb spd_cb;
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if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
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printf("Sorry, I don't know how to configure DDR3A.\n"
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"Bye :(\n");
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for (;;)
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;
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}
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printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
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printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
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if (spd_cb.ddrspdclock == 1600)
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init_pll(&ddr3_400);
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else
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init_pll(&ddr3_333);
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/* Reset DDR3 PHY after PLL enabled */
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ddr3_reset_ddrphy();
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spd_cb.phy_cfg.zq0cr1 |= 0x10000;
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spd_cb.phy_cfg.zq1cr1 |= 0x10000;
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spd_cb.phy_cfg.zq2cr1 |= 0x10000;
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
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printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
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return (u32)spd_cb.ddr_size_gbyte;
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}
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