upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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47 lines
1.4 KiB
47 lines
1.4 KiB
/*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7794 CPG Core Clocks */
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#define R8A7794_CLK_Z2 0
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#define R8A7794_CLK_ZG 1
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#define R8A7794_CLK_ZTR 2
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#define R8A7794_CLK_ZTRD2 3
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#define R8A7794_CLK_ZT 4
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#define R8A7794_CLK_ZX 5
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#define R8A7794_CLK_ZS 6
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#define R8A7794_CLK_HP 7
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#define R8A7794_CLK_I 8
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#define R8A7794_CLK_B 9
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#define R8A7794_CLK_LB 10
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#define R8A7794_CLK_P 11
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#define R8A7794_CLK_CL 12
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#define R8A7794_CLK_CP 13
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#define R8A7794_CLK_M2 14
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#define R8A7794_CLK_ADSP 15
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#define R8A7794_CLK_ZB3 16
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#define R8A7794_CLK_ZB3D2 17
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#define R8A7794_CLK_DDR 18
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#define R8A7794_CLK_SDH 19
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#define R8A7794_CLK_SD0 20
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#define R8A7794_CLK_SD2 21
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#define R8A7794_CLK_SD3 22
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#define R8A7794_CLK_MMC0 23
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#define R8A7794_CLK_MP 24
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#define R8A7794_CLK_QSPI 25
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#define R8A7794_CLK_CPEX 26
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#define R8A7794_CLK_RCAN 27
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#define R8A7794_CLK_R 28
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#define R8A7794_CLK_OSC 29
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#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
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