upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/arch/x86/include/asm/pci.h

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/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PCI_I386_H_
#define _PCI_I386_H_
#include <pci.h>
/* bus mapping constants (used for PCI core initialization) */
#define PCI_REG_ADDR 0xcf8
#define PCI_REG_DATA 0xcfc
#define PCI_CFG_EN 0x80000000
#ifndef __ASSEMBLY__
#define DEFINE_PCI_DEVICE_TABLE(_table) \
const struct pci_device_id _table[]
struct pci_controller;
void pci_setup_type1(struct pci_controller *hose);
/*
* Simple PCI access routines - these work from either the early PCI hose
* or the 'real' one, created after U-Boot has memory available
*/
unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where);
unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where);
unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where);
void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size);
int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong value, enum pci_size_t size);
/**
* Assign IRQ number to a PCI device
*
* This function assigns IRQ for a PCI device. If the device does not exist
* or does not require interrupts then this function has no effect.
*
* @bus: PCI bus number
* @device: PCI device number
* @irq: An array of IRQ numbers that are assigned to INTA through
* INTD of this PCI device.
*/
void pci_assign_irqs(int bus, int device, u8 irq[4]);
#endif /* __ASSEMBLY__ */
#endif /* _PCI_I386_H_ */