upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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276 lines
7.3 KiB
276 lines
7.3 KiB
/*
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* (C) Copyright 2003-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <net.h>
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#include <asm/processor.h>
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start(int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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#endif /* SDRAM_DDR */
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/* precharge all banks */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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#endif /* !CONFIG_SYS_RAMBOOT */
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phys_size_t initdram(int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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uint svr, pvr;
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#ifndef CONFIG_SYS_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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#endif /* SDRAM_DDR */
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else
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dramsize = test2;
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0)
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
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else
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*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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/* let SDRAM CS1 start right after CS0 */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
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/* find RAM size using SDRAM CS1 only */
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if (!dramsize)
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sdram_start(0);
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test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
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if (!dramsize) {
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sdram_start(1);
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test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
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}
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if (test1 > test2) {
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sdram_start(0);
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dramsize2 = test1;
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} else
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dramsize2 = test2;
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/* memory smaller than 1MB is impossible */
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if (dramsize2 < (1 << 20))
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dramsize2 = 0;
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/* set SDRAM CS1 size according to the amount of RAM found */
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if (dramsize2 > 0)
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
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| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
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else
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
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if (dramsize >= 0x13)
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dramsize = (1 << (dramsize - 0x13)) << 20;
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else
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dramsize = 0;
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
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if (dramsize2 >= 0x13)
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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else
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dramsize2 = 0;
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#endif /* CONFIG_SYS_RAMBOOT */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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svr = get_svr();
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pvr = get_pvr();
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if ((SVR_MJREV(svr) >= 2) &&
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(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
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*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
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__asm__ volatile ("sync");
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}
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return dramsize + dramsize2;
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}
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int checkboard (void)
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{
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puts("Board: MarelV38B\n");
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return 0;
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_HW_WATCHDOG
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/*
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* Enable and configure the direction (output) of PSC3_9 - watchdog
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* reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
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* Manual.
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*/
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
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#endif /* CONFIG_HW_WATCHDOG */
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return 0;
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}
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int board_early_init_r(void)
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{
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/*
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* Now, when we are in RAM, enable flash write access for the
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* detection process. Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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/*
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* Enable GPIO_WKUP_7 to "read the status of the actual power
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* situation". Default direction is input, so no need to set it
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* explicitly.
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*/
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
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return 0;
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}
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extern void board_get_enetaddr(uchar *enetaddr);
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int misc_init_r(void)
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{
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uchar enetaddr[6];
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if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
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board_get_enetaddr(enetaddr);
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eth_setenv_enetaddr("ethaddr", enetaddr);
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}
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return 0;
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}
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#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
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void init_ide_reset(void)
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{
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debug("init_ide_reset\n");
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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/* Deassert reset */
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
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}
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void ide_set_reset(int idereset)
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{
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debug("ide_reset(%d)\n", idereset);
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
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/* Make a delay. MPC5200 spec says 25 usec min */
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udelay(500000);
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} else
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
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}
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#endif
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#ifdef CONFIG_HW_WATCHDOG
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void hw_watchdog_reset(void)
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{
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/*
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* MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
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* we need a positive or negative transition on WDI i.e., our PSC3_9.
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*/
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
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}
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#endif /* CONFIG_HW_WATCHDOG */
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