upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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257 lines
7.4 KiB
257 lines
7.4 KiB
/*
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* Port Masks
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*/
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#ifndef __BFIN_PERIPHERAL_PORT__
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#define __BFIN_PERIPHERAL_PORT__
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/* PORTx_MUX Masks */
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#define PORT_x_MUX_0_MASK 0x00000003
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#define PORT_x_MUX_1_MASK 0x0000000C
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#define PORT_x_MUX_2_MASK 0x00000030
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#define PORT_x_MUX_3_MASK 0x000000C0
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#define PORT_x_MUX_4_MASK 0x00000300
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#define PORT_x_MUX_5_MASK 0x00000C00
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#define PORT_x_MUX_6_MASK 0x00003000
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#define PORT_x_MUX_7_MASK 0x0000C000
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#define PORT_x_MUX_8_MASK 0x00030000
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#define PORT_x_MUX_9_MASK 0x000C0000
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#define PORT_x_MUX_10_MASK 0x00300000
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#define PORT_x_MUX_11_MASK 0x00C00000
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#define PORT_x_MUX_12_MASK 0x03000000
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#define PORT_x_MUX_13_MASK 0x0C000000
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#define PORT_x_MUX_14_MASK 0x30000000
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#define PORT_x_MUX_15_MASK 0xC0000000
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#define PORT_x_MUX_FUNC_1 (0x0)
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#define PORT_x_MUX_FUNC_2 (0x1)
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#define PORT_x_MUX_FUNC_3 (0x2)
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#define PORT_x_MUX_FUNC_4 (0x3)
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#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
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#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
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#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
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#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
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#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
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#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
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#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
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#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
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#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
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#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
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#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
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#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
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#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
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#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
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#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
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#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
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#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
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#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
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#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
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#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
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#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
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#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
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#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
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#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
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#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
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#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
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#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
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#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
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#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
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#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
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#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
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#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
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#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16)
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#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16)
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#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16)
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#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16)
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#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18)
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#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18)
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#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18)
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#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18)
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#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20)
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#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20)
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#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20)
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#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20)
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#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22)
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#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22)
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#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22)
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#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22)
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#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24)
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#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24)
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#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24)
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#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24)
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#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26)
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#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26)
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#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26)
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#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26)
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#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28)
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#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28)
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#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28)
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#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28)
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#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30)
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#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30)
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#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
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#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
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/* Port A Masks */
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#define PA0 0x0001
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#define PA1 0x0002
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#define PA2 0x0004
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#define PA3 0x0008
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#define PA4 0x0010
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#define PA5 0x0020
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#define PA6 0x0040
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#define PA7 0x0080
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#define PA8 0x0100
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#define PA9 0x0200
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#define PA10 0x0400
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#define PA11 0x0800
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#define PA12 0x1000
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#define PA13 0x2000
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#define PA14 0x4000
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#define PA15 0x8000
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/* Port B Masks */
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#define PB0 0x0001
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#define PB1 0x0002
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#define PB2 0x0004
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#define PB3 0x0008
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#define PB4 0x0010
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#define PB5 0x0020
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#define PB6 0x0040
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#define PB7 0x0080
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#define PB8 0x0100
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#define PB9 0x0200
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#define PB10 0x0400
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#define PB11 0x0800
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#define PB12 0x1000
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#define PB13 0x2000
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#define PB14 0x4000
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#define PB15 0x8000
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/* Port C Masks */
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#define PC0 0x0001
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#define PC1 0x0002
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#define PC2 0x0004
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#define PC3 0x0008
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#define PC4 0x0010
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#define PC5 0x0020
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#define PC6 0x0040
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#define PC7 0x0080
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#define PC8 0x0100
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#define PC9 0x0200
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#define PC10 0x0400
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#define PC11 0x0800
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#define PC12 0x1000
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#define PC13 0x2000
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#define PC14 0x4000
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#define PC15 0x8000
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/* Port F Masks */
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#define PD0 0x0001
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#define PD1 0x0002
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#define PD2 0x0004
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#define PD3 0x0008
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#define PD4 0x0010
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#define PD5 0x0020
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#define PD6 0x0040
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#define PD7 0x0080
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#define PD8 0x0100
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#define PD9 0x0200
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#define PD10 0x0400
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#define PD11 0x0800
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#define PD12 0x1000
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#define PD13 0x2000
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#define PD14 0x4000
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#define PD15 0x8000
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/* Port F Masks */
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#define PE0 0x0001
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#define PE1 0x0002
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#define PE2 0x0004
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#define PE3 0x0008
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#define PE4 0x0010
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#define PE5 0x0020
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#define PE6 0x0040
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#define PE7 0x0080
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#define PE8 0x0100
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#define PE9 0x0200
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#define PE10 0x0400
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#define PE11 0x0800
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#define PE12 0x1000
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#define PE13 0x2000
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#define PE14 0x4000
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#define PE15 0x8000
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/* Port F Masks */
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#define PF0 0x0001
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#define PF1 0x0002
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#define PF2 0x0004
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#define PF3 0x0008
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#define PF4 0x0010
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#define PF5 0x0020
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#define PF6 0x0040
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#define PF7 0x0080
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#define PF8 0x0100
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#define PF9 0x0200
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#define PF10 0x0400
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#define PF11 0x0800
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#define PF12 0x1000
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#define PF13 0x2000
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#define PF14 0x4000
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#define PF15 0x8000
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/* Port G Masks */
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#define PG0 0x0001
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#define PG1 0x0002
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#define PG2 0x0004
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#define PG3 0x0008
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#define PG4 0x0010
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#define PG5 0x0020
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#define PG6 0x0040
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#define PG7 0x0080
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#define PG8 0x0100
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#define PG9 0x0200
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#define PG10 0x0400
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#define PG11 0x0800
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#define PG12 0x1000
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#define PG13 0x2000
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#define PG14 0x4000
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#define PG15 0x8000
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/* Port H Masks */
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#define PH0 0x0001
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#define PH1 0x0002
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#define PH2 0x0004
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#define PH3 0x0008
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#define PH4 0x0010
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#define PH5 0x0020
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#define PH6 0x0040
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#define PH7 0x0080
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#define PH8 0x0100
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#define PH9 0x0200
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#define PH10 0x0400
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#define PH11 0x0800
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#define PH12 0x1000
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#define PH13 0x2000
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#define PH14 0x4000
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#define PH15 0x8000
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/* Port J Masks */
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#define PJ0 0x0001
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#define PJ1 0x0002
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#define PJ2 0x0004
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#define PJ3 0x0008
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#define PJ4 0x0010
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#define PJ5 0x0020
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#define PJ6 0x0040
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#define PJ7 0x0080
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#define PJ8 0x0100
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#define PJ9 0x0200
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#define PJ10 0x0400
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#define PJ11 0x0800
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#define PJ12 0x1000
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#define PJ13 0x2000
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#define PJ14 0x4000
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#define PJ15 0x8000
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#endif
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