upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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126 lines
2.8 KiB
126 lines
2.8 KiB
/*
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* Copyright (C) 2012-2014 Panasonic Corporation
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* Copyright (C) 2015 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/armv7.h>
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#include <mach/ssc-regs.h>
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#ifdef CONFIG_UNIPHIER_L2CACHE_ON
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static void uniphier_cache_maint_all(u32 operation)
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{
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/* try until the command is successfully set */
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do {
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writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
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} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
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/* wait until the operation is completed */
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while (readl(SSCOLPQS) != SSCOLPQS_EF)
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;
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/* clear the complete notification flag */
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writel(SSCOLPQS_EF, SSCOLPQS);
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writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
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readl(SSCOPE); /* need a read back to confirm */
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}
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void v7_outer_cache_flush_all(void)
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{
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uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
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}
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void v7_outer_cache_inval_all(void)
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{
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uniphier_cache_maint_all(SSCOQM_CM_INV);
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}
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static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
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{
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/* try until the command is successfully set */
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do {
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writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
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writel(start, SSCOQAD);
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writel(size, SSCOQSZ);
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} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
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/* wait until the operation is completed */
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while (readl(SSCOLPQS) != SSCOLPQS_EF)
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;
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/* clear the complete notification flag */
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writel(SSCOLPQS_EF, SSCOLPQS);
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}
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static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
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{
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u32 size;
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/*
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* If start address is not aligned to cache-line,
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* do cache operation for the first cache-line
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*/
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start = start & ~(SSC_LINE_SIZE - 1);
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if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
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/* this means cache operation for all range */
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uniphier_cache_maint_all(operation);
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return;
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}
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/*
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* If end address is not aligned to cache-line,
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* do cache operation for the last cache-line
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*/
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size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
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while (size) {
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u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
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SSC_RANGE_OP_MAX_SIZE : size;
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__uniphier_cache_maint_range(start, chunk_size, operation);
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start += chunk_size;
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size -= chunk_size;
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}
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writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
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readl(SSCOPE); /* need a read back to confirm */
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}
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void v7_outer_cache_flush_range(u32 start, u32 end)
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{
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uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
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}
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void v7_outer_cache_inval_range(u32 start, u32 end)
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{
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uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
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}
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void v7_outer_cache_enable(void)
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{
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u32 tmp;
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tmp = readl(SSCC);
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tmp |= SSCC_ON;
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writel(tmp, SSCC);
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}
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#endif
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void v7_outer_cache_disable(void)
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{
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u32 tmp;
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tmp = readl(SSCC);
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tmp &= ~SSCC_ON;
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writel(tmp, SSCC);
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}
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void enable_caches(void)
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{
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dcache_enable();
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}
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