upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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71 lines
2.1 KiB
71 lines
2.1 KiB
/*
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*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#ifdef CONFIG_SYS_MX31_UART1
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void mx31_uart1_hw_init(void)
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{
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
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}
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#endif
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#ifdef CONFIG_SYS_MX31_UART2
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void mx31_uart2_hw_init(void)
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{
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/* setup pins for UART2 */
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mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
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mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
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mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
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mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
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}
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#endif
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#ifdef CONFIG_MXC_SPI
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/*
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* Note: putting several spi setups here makes no sense as they may differ
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* at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
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*/
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void mx31_spi2_hw_init(void)
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{
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/* SPI2 */
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mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
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mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
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mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
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mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
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mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
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mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
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mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
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/* start SPI2 clock */
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
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}
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#endif
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