upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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407 lines
12 KiB
407 lines
12 KiB
/*
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* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
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* (C) Copyright 2007 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* Derived from the MPC83xx header.
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*/
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#ifndef __MPC512X_H__
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#define __MPC512X_H__
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#include <config.h>
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#if defined(CONFIG_E300)
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#include <asm/e300.h>
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#endif
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/* System reset offset (PowerPC standard)
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*/
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#define EXC_OFF_SYS_RESET 0x0100
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#define _START_OFFSET EXC_OFF_SYS_RESET
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/* IMMRBAR - Internal Memory Register Base Address
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*/
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#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
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#define IMMRBAR 0x0000 /* Register offset to immr */
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#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
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#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
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/* LAWBAR - Local Access Window Base Address Register
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*/
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#define LPBAW 0x0020 /* Register offset to immr */
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#define LPCS0AW 0x0024
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#define LPCS1AW 0x0028
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#define LPCS2AW 0x002C
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#define LPCS3AW 0x0030
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#define LPCS4AW 0x0034
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#define LPCS5AW 0x0038
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#define LPCS6AW 0x003C
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#define LPCA7AW 0x0040
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#define SRAMBAR 0x00C4
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#define LPC_OFFSET 0x10000
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#define CS0_CONFIG 0x00000
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#define CS1_CONFIG 0x00004
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#define CS2_CONFIG 0x00008
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#define CS3_CONFIG 0x0000C
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#define CS4_CONFIG 0x00010
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#define CS5_CONFIG 0x00014
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#define CS6_CONFIG 0x00018
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#define CS7_CONFIG 0x0001C
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#define CS_CTRL 0x00020
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#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
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#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */
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/* SPRIDR - System Part and Revision ID Register
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*/
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#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
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#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
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#define SPR_5121E 0x80180000
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/* SPCR - System Priority Configuration Register
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*/
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#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
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#define SPCR_PCIHPE_SHIFT (31-3)
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#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */
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#define SPCR_PCIPR_SHIFT (31-7)
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#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */
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#define SPCR_TBEN_SHIFT (31-9)
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#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */
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#define SPCR_COREPR_SHIFT (31-11)
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/* SWCRR - System Watchdog Control Register
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*/
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#define SWCRR 0x0904 /* Register offset to immr */
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#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
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#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
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#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
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#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
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#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
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/* SWCNR - System Watchdog Counter Register
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*/
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#define SWCNR 0x0908 /* Register offset to immr */
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#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */
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#define SWCNR_RES ~(SWCNR_SWCN)
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/* SWSRR - System Watchdog Service Register
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*/
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#define SWSRR 0x090E /* Register offset to immr */
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/* ACR - Arbiter Configuration Register
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*/
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#define ACR_COREDIS 0x10000000 /* Core disable */
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#define ACR_COREDIS_SHIFT (31-7)
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#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
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#define ACR_PIPE_DEP_SHIFT (31-15)
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#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
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#define ACR_PCI_RPTCNT_SHIFT (31-19)
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#define ACR_RPTCNT 0x00000700 /* Repeat count */
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#define ACR_RPTCNT_SHIFT (31-23)
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#define ACR_APARK 0x00000030 /* Address parking */
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#define ACR_APARK_SHIFT (31-27)
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#define ACR_PARKM 0x0000000F /* Parking master */
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#define ACR_PARKM_SHIFT (31-31)
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/* ATR - Arbiter Timers Register
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*/
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#define ATR_DTO 0x00FF0000 /* Data time out */
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#define ATR_ATO 0x000000FF /* Address time out */
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/* AER - Arbiter Event Register
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*/
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#define AER_ETEA 0x00000020 /* Transfer error */
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#define AER_RES 0x00000010 /* Reserved transfer type */
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#define AER_ECW 0x00000008 /* External control word transfer type */
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#define AER_AO 0x00000004 /* Address Only transfer type */
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#define AER_DTO 0x00000002 /* Data time out */
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#define AER_ATO 0x00000001 /* Address time out */
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/* AEATR - Arbiter Event Address Register
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*/
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#define AEATR_EVENT 0x07000000 /* Event type */
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#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
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#define AEATR_TBST 0x00000800 /* Transfer burst */
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#define AEATR_TSIZE 0x00000700 /* Transfer Size */
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#define AEATR_TTYPE 0x0000001F /* Transfer Type */
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/* RSR - Reset Status Register
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*/
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#define RSR_SWSR 0x00002000 /* software soft reset */
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#define RSR_SWSR_SHIFT 13
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#define RSR_SWHR 0x00001000 /* software hard reset */
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#define RSR_SWHR_SHIFT 12
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#define RSR_JHRS 0x00000200 /* jtag hreset */
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#define RSR_JHRS_SHIFT 9
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#define RSR_JSRS 0x00000100 /* jtag sreset status */
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#define RSR_JSRS_SHIFT 8
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#define RSR_CSHR 0x00000010 /* checkstop reset status */
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#define RSR_CSHR_SHIFT 4
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#define RSR_SWRS 0x00000008 /* software watchdog reset status */
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#define RSR_SWRS_SHIFT 3
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#define RSR_BMRS 0x00000004 /* bus monitop reset status */
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#define RSR_BMRS_SHIFT 2
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#define RSR_SRS 0x00000002 /* soft reset status */
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#define RSR_SRS_SHIFT 1
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#define RSR_HRS 0x00000001 /* hard reset status */
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#define RSR_HRS_SHIFT 0
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#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\
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RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
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RSR_BMRS | RSR_SRS | RSR_HRS)
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/* RMR - Reset Mode Register
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*/
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#define RMR_CSRE 0x00000001 /* checkstop reset enable */
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#define RMR_CSRE_SHIFT 0
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#define RMR_RES ~(RMR_CSRE)
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/* RCR - Reset Control Register
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*/
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#define RCR_SWHR 0x00000002 /* software hard reset */
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#define RCR_SWSR 0x00000001 /* software soft reset */
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#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
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/* RCER - Reset Control Enable Register
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*/
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#define RCER_CRE 0x00000001 /* software hard reset */
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#define RCER_RES ~(RCER_CRE)
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/* SPMR - System PLL Mode Register
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*/
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#define SPMR_SPMF 0x0F000000
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#define SPMR_SPMF_SHIFT 24
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#define SPMR_CPMF 0x000F0000
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#define SPMR_CPMF_SHIFT 16
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/* SCFR1 System Clock Frequency Register 1
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*/
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#define SCFR1_IPS_DIV 0x3
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#define SCFR1_IPS_DIV_MASK 0x03800000
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#define SCFR1_IPS_DIV_SHIFT 23
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/* SCFR2 System Clock Frequency Register 2
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*/
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#define SCFR2_SYS_DIV 0xFC000000
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#define SCFR2_SYS_DIV_SHIFT 26
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/* SCCR - System Clock Control Registers
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*/
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/* System Clock Control Register 1 commands */
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#define CLOCK_SCCR1_CFG_EN 0x80000000
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#define CLOCK_SCCR1_LPC_EN 0x40000000
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#define CLOCK_SCCR1_NFC_EN 0x20000000
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#define CLOCK_SCCR1_PATA_EN 0x10000000
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#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn))
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#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000
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#define CLOCK_SCCR1_SATA_EN 0x00004000
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#define CLOCK_SCCR1_FEC_EN 0x00002000
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#define CLOCK_SCCR1_TPR_EN 0x00001000
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#define CLOCK_SCCR1_PCI_EN 0x00000800
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#define CLOCK_SCCR1_DDR_EN 0x00000400
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/* System Clock Control Register 2 commands */
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#define CLOCK_SCCR2_DIU_EN 0x80000000
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#define CLOCK_SCCR2_AXE_EN 0x40000000
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#define CLOCK_SCCR2_MEM_EN 0x20000000
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#define CLOCK_SCCR2_USB2_EN 0x10000000
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#define CLOCK_SCCR2_USB1_EN 0x08000000
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#define CLOCK_SCCR2_I2C_EN 0x04000000
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#define CLOCK_SCCR2_BDLC_EN 0x02000000
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#define CLOCK_SCCR2_SDHC_EN 0x01000000
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#define CLOCK_SCCR2_SPDIF_EN 0x00800000
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#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000
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#define CLOCK_SCCR2_MBX_EN 0x00200000
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#define CLOCK_SCCR2_MBX_3D_EN 0x00100000
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#define CLOCK_SCCR2_IIM_EN 0x00080000
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/* PSC FIFO Command values */
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#define PSC_FIFO_RESET_SLICE 0x80
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#define PSC_FIFO_ENABLE_SLICE 0x01
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/* PSC FIFO Controller Command values */
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#define FIFOC_ENABLE_CLOCK_GATE 0x01
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#define FIFOC_DISABLE_CLOCK_GATE 0x00
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/* PSC FIFO status */
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#define PSC_FIFO_EMPTY 0x01
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/* PSC Command values */
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#define PSC_RX_ENABLE 0x01
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#define PSC_RX_DISABLE 0x02
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#define PSC_TX_ENABLE 0x04
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#define PSC_TX_DISABLE 0x08
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#define PSC_SEL_MODE_REG_1 0x10
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#define PSC_RST_RX 0x20
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#define PSC_RST_TX 0x30
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#define PSC_RST_ERR_STAT 0x40
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#define PSC_RST_BRK_CHG_INT 0x50
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#define PSC_START_BRK 0x60
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#define PSC_STOP_BRK 0x70
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/* PSC status register bits */
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#define PSC_SR_CDE 0x0080
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#define PSC_SR_TXEMP 0x0800
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#define PSC_SR_OE 0x1000
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#define PSC_SR_PE 0x2000
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#define PSC_SR_FE 0x4000
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#define PSC_SR_RB 0x8000
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/* PSC mode fields */
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#define PSC_MODE_5_BITS 0x00
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#define PSC_MODE_6_BITS 0x01
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#define PSC_MODE_7_BITS 0x02
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#define PSC_MODE_8_BITS 0x03
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#define PSC_MODE_PAREVEN 0x00
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#define PSC_MODE_PARODD 0x04
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#define PSC_MODE_PARFORCE 0x08
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#define PSC_MODE_PARNONE 0x10
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#define PSC_MODE_ENTIMEOUT 0x20
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#define PSC_MODE_RXRTS 0x80
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#define PSC_MODE_1_STOPBIT 0x07
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/*
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* Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
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*
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* NOTE: individual PSC units are free to use whatever area (and size) of the
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* FIFOC internal memory, so make sure memory areas for FIFO slices used by
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* different PSCs do not overlap!
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*
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* Overall size of FIFOC memory is not documented in the MPC5121e RM, but
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* tests indicate that it is 1024 words total.
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*/
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#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */
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#define FIFOC_PSC0_TX_ADDR 0x0
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#define FIFOC_PSC0_RX_SIZE 0x0
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#define FIFOC_PSC0_RX_ADDR 0x0
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#define FIFOC_PSC1_TX_SIZE 0x0
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#define FIFOC_PSC1_TX_ADDR 0x0
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#define FIFOC_PSC1_RX_SIZE 0x0
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#define FIFOC_PSC1_RX_ADDR 0x0
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#define FIFOC_PSC2_TX_SIZE 0x0
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#define FIFOC_PSC2_TX_ADDR 0x0
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#define FIFOC_PSC2_RX_SIZE 0x0
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#define FIFOC_PSC2_RX_ADDR 0x0
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#define FIFOC_PSC3_TX_SIZE 0x04
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#define FIFOC_PSC3_TX_ADDR 0x0
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#define FIFOC_PSC3_RX_SIZE 0x04
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#define FIFOC_PSC3_RX_ADDR 0x10
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#define FIFOC_PSC4_TX_SIZE 0x0
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#define FIFOC_PSC4_TX_ADDR 0x0
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#define FIFOC_PSC4_RX_SIZE 0x0
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#define FIFOC_PSC4_RX_ADDR 0x0
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#define FIFOC_PSC5_TX_SIZE 0x0
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#define FIFOC_PSC5_TX_ADDR 0x0
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#define FIFOC_PSC5_RX_SIZE 0x0
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#define FIFOC_PSC5_RX_ADDR 0x0
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#define FIFOC_PSC6_TX_SIZE 0x0
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#define FIFOC_PSC6_TX_ADDR 0x0
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#define FIFOC_PSC6_RX_SIZE 0x0
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#define FIFOC_PSC6_RX_ADDR 0x0
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#define FIFOC_PSC7_TX_SIZE 0x0
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#define FIFOC_PSC7_TX_ADDR 0x0
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#define FIFOC_PSC7_RX_SIZE 0x0
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#define FIFOC_PSC7_RX_ADDR 0x0
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#define FIFOC_PSC8_TX_SIZE 0x0
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#define FIFOC_PSC8_TX_ADDR 0x0
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#define FIFOC_PSC8_RX_SIZE 0x0
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#define FIFOC_PSC8_RX_ADDR 0x0
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#define FIFOC_PSC9_TX_SIZE 0x0
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#define FIFOC_PSC9_TX_ADDR 0x0
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#define FIFOC_PSC9_RX_SIZE 0x0
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#define FIFOC_PSC9_RX_ADDR 0x0
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#define FIFOC_PSC10_TX_SIZE 0x0
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#define FIFOC_PSC10_TX_ADDR 0x0
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#define FIFOC_PSC10_RX_SIZE 0x0
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#define FIFOC_PSC10_RX_ADDR 0x0
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#define FIFOC_PSC11_TX_SIZE 0x0
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#define FIFOC_PSC11_TX_ADDR 0x0
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#define FIFOC_PSC11_RX_SIZE 0x0
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#define FIFOC_PSC11_RX_ADDR 0x0
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/* IO Control Register
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*/
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/* Indexes in regs array */
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#define MEM_IDX 0x00
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#define PATA_CE1_IDX 0x2e
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#define PATA_CE2_IDX 0x2f
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#define PATA_ISOLATE_IDX 0x30
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#define PATA_IOR_IDX 0x31
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#define PATA_IOW_IDX 0x32
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#define PATA_IOCHRDY_IDX 0x33
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#define PATA_INTRQ_IDX 0x34
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#define PATA_DRQ_IDX 0x35
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#define PATA_DACK_IDX 0x36
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#define SPDIF_TXCLOCK_IDX 0x73
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#define SPDIF_TX_IDX 0x74
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#define SPDIF_RX_IDX 0x75
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#define PSC0_0_IDX 0x83
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#define PSC0_1_IDX 0x84
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#define PSC0_2_IDX 0x85
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#define PSC0_3_IDX 0x86
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#define PSC0_4_IDX 0x87
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#define PSC1_0_IDX 0x88
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#define PSC1_1_IDX 0x89
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#define PSC1_2_IDX 0x8a
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#define PSC1_3_IDX 0x8b
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#define PSC1_4_IDX 0x8c
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#define PSC2_0_IDX 0x8d
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#define PSC2_1_IDX 0x8e
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#define PSC2_2_IDX 0x8f
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#define PSC2_3_IDX 0x90
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#define PSC2_4_IDX 0x91
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#define IOCTRL_FUNCMUX_SHIFT 7
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#define IOCTRL_FUNCMUX_FEC 1
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#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT)
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/* Set for DDR */
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#define IOCTRL_MUX_DDR 0x00000036
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/* Register Offset Base */
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#define MPC512X_FEC (CFG_IMMR + 0x02800)
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/* Number of I2C buses */
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#define I2C_BUS_CNT 3
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/* I2Cn control register bits */
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#define I2C_EN 0x80
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#define I2C_IEN 0x40
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#define I2C_STA 0x20
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#define I2C_TX 0x10
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#define I2C_TXAK 0x08
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#define I2C_RSTA 0x04
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#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
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/* I2Cn status register bits */
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#define I2C_CF 0x80
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#define I2C_AAS 0x40
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#define I2C_BB 0x20
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#define I2C_AL 0x10
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#define I2C_SRW 0x04
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#define I2C_IF 0x02
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#define I2C_RXAK 0x01
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#endif /* __MPC512X_H__ */
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