upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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321 lines
8.8 KiB
321 lines
8.8 KiB
/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num);
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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extern fixed_ddr_parm_t fixed_ddr_parm_0[];
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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extern fixed_ddr_parm_t fixed_ddr_parm_1[];
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#endif
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phys_size_t fixed_sdram(void)
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{
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int i;
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sys_info_t sysinfo;
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char buf[32];
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fsl_ddr_cfg_regs_t ddr_cfg_regs;
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phys_size_t ddr_size;
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unsigned int lawbar1_target_id;
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get_sys_info(&sysinfo);
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
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if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
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(sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
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memcpy(&ddr_cfg_regs,
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fixed_ddr_parm_0[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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break;
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}
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}
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if (fixed_ddr_parm_0[i].max_freq == 0)
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panic("Unsupported DDR data rate %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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memcpy(&ddr_cfg_regs,
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fixed_ddr_parm_1[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
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#endif
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/*
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* setup laws for DDR. If not interleaving, presuming half memory on
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* DDR1 and the other half on DDR2
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*/
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if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size,
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LAW_TRGT_IF_DDR_INTRLV) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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} else {
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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/* We require both controllers have identical DIMMs */
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lawbar1_target_id = LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size / 2,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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lawbar1_target_id = LAW_TRGT_IF_DDR_2;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
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ddr_size / 2,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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#else
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lawbar1_target_id = LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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#endif
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}
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return ddr_size;
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}
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static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
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{
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int ret;
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ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
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if (ret) {
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debug("DDR: failed to read SPD from address %u\n", i2c_address);
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memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
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}
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}
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unsigned int fsl_ddr_get_mem_data_rate(void)
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{
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return get_ddr_freq(0);
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}
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void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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unsigned int i;
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unsigned int i2c_address = 0;
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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if (ctrl_num == 0 && i == 0)
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i2c_address = SPD_EEPROM_ADDRESS1;
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else if (ctrl_num == 1 && i == 0)
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i2c_address = SPD_EEPROM_ADDRESS2;
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get_spd(&(ctrl_dimms_spd[i]), i2c_address);
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}
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}
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typedef struct {
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u32 datarate_mhz_low;
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u32 datarate_mhz_high;
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u32 n_ranks;
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u32 clk_adjust;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2T;
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} board_specific_parameters_t;
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/* ranges for parameters:
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* wr_data_delay = 0-6
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* clk adjust = 0-8
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* cpo 2-0x1E (30)
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*/
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/* XXX: these values need to be checked for all interleaving modes. */
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/* XXX: No reliable dual-rank 800 MHz setting has been found. It may
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* seem reliable, but errors will appear when memory intensive
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* program is run. */
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/* XXX: Single rank at 800 MHz is OK. */
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const board_specific_parameters_t board_specific_parameters[][30] = {
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{
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/* memory controller 0 */
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/* lo| hi| num| clk| cpo|wrdata|2T */
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/* mhz| mhz|ranks|adjst| | delay| */
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{ 0, 333, 4, 6, 7, 3, 0},
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{334, 400, 4, 6, 9, 3, 0},
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{401, 549, 4, 6, 11, 3, 0},
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{550, 680, 4, 1, 10, 5, 0},
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{681, 850, 4, 1, 12, 5, 0},
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{851, 1050, 4, 1, 12, 5, 0},
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{1051, 1250, 4, 1, 15, 4, 0},
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{1251, 1350, 4, 1, 15, 4, 0},
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{ 0, 333, 2, 6, 7, 3, 0},
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{334, 400, 2, 6, 9, 3, 0},
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{401, 549, 2, 6, 11, 3, 0},
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{550, 680, 2, 1, 10, 5, 0},
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{681, 850, 2, 1, 12, 5, 0},
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{851, 1050, 2, 1, 12, 5, 0},
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{1051, 1250, 2, 1, 15, 4, 0},
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{1251, 1350, 2, 1, 15, 4, 0},
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{ 0, 333, 1, 6, 7, 3, 0},
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{334, 400, 1, 6, 9, 3, 0},
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{401, 549, 1, 6, 11, 3, 0},
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{550, 680, 1, 1, 10, 5, 0},
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{681, 850, 1, 1, 12, 5, 0}
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},
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{
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/* memory controller 1 */
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/* lo| hi| num| clk| cpo|wrdata|2T */
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/* mhz| mhz|ranks|adjst| | delay| */
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{ 0, 333, 4, 6, 7, 3, 0},
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{334, 400, 4, 6, 9, 3, 0},
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{401, 549, 4, 6, 11, 3, 0},
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{550, 680, 4, 1, 10, 5, 0},
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{681, 850, 4, 1, 12, 5, 0},
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{851, 1050, 4, 1, 12, 5, 0},
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{1051, 1250, 4, 1, 15, 4, 0},
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{1251, 1350, 4, 1, 15, 4, 0},
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{ 0, 333, 2, 6, 7, 3, 0},
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{334, 400, 2, 6, 9, 3, 0},
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{401, 549, 2, 6, 11, 3, 0},
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{550, 680, 2, 1, 11, 6, 0},
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{681, 850, 2, 1, 13, 6, 0},
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{851, 1050, 2, 1, 13, 6, 0},
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{1051, 1250, 2, 1, 15, 4, 0},
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{1251, 1350, 2, 1, 15, 4, 0},
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{ 0, 333, 1, 6, 7, 3, 0},
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{334, 400, 1, 6, 9, 3, 0},
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{401, 549, 1, 6, 11, 3, 0},
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{550, 680, 1, 1, 11, 6, 0},
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{681, 850, 1, 1, 13, 6, 0}
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}
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const board_specific_parameters_t *pbsp =
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&(board_specific_parameters[ctrl_num][0]);
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u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
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sizeof(board_specific_parameters[0][0]);
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u32 i;
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ulong ddr_freq;
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/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
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* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
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* there are two dimms in the controller, set odt_rd_cfg to 3 and
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* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
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*/
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i&1) { /* odd CS */
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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} else { /* even CS */
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if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
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popts->cs_local_opts[i].odt_rd_cfg = 3;
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popts->cs_local_opts[i].odt_wr_cfg = 3;
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}
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}
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}
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < num_params; i++) {
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if (ddr_freq >= pbsp->datarate_mhz_low &&
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ddr_freq <= pbsp->datarate_mhz_high &&
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pdimm->n_ranks == pbsp->n_ranks) {
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popts->cpo_override = 0xff; /* force auto CPO calibration */
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popts->write_data_delay = 2;
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popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */
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popts->twoT_en = pbsp->force_2T;
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}
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pbsp++;
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xa;
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popts->wrlvl_start = 0x7;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 1;
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popts->rtt_override_value = DDR3_RTT_120_OHM;
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popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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int use_spd = 0;
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puts("Initializing....");
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#ifdef CONFIG_DDR_SPD
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/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
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if (hwconfig_sub("fsl_ddr", "sdram")) {
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if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
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use_spd = 1;
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else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
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use_spd = 0;
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else
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use_spd = 1;
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} else
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use_spd = 1;
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#endif
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if (use_spd) {
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puts("using SPD\n");
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dram_size = fsl_ddr_sdram();
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} else {
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puts("using fixed parameters\n");
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dram_size = fixed_sdram();
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}
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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