upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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68 lines
2.6 KiB
68 lines
2.6 KiB
/*
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* Copyright 2008,2010 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
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* 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M
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* else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
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* 0x8000_0000 0x9fff_ffff RapidIO 512M
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* endif
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* (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
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* 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K
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* 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K
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* 0xffe0_0000 0xffef_ffff CCSRBAR 1M
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* 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
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* 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
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*
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* Notes:
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* CCSRBAR doesn't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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struct law_entry law_table[] = {
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#if !defined(CONFIG_SPD_EEPROM)
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
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#endif
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#ifdef CONFIG_PCI
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
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SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
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#elif defined(CONFIG_RIO)
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SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
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#endif
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SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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