upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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466 lines
13 KiB
466 lines
13 KiB
/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <fsl_pmic.h>
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#include <mc13892.h>
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DECLARE_GLOBAL_DATA_PTR;
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static u32 system_rev;
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR, 1},
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{MMC_SDHC2_BASE_ADDR, 1},
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};
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#endif
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u32 get_board_rev(void)
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{
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return system_rev;
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
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mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
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mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
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}
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
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/*FEC_MDC*/
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mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
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/* FEC RDATA[3] */
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mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
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/* FEC RDATA[2] */
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mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
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/* FEC RDATA[1] */
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mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
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/* FEC RDATA[0] */
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mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
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/* FEC TDATA[3] */
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mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
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/* FEC TDATA[2] */
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mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
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/* FEC TDATA[1] */
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mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
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/* FEC TDATA[0] */
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mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
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/* FEC TX_EN */
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mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
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/* FEC TX_ER */
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mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
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/* FEC TX_CLK */
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mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
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/* FEC TX_COL */
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mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
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/* FEC RX_CLK */
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mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
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/* FEC RX_CRS */
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mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
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/* FEC RX_ER */
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mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
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/* FEC RX_DV */
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mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
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}
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#ifdef CONFIG_MXC_SPI
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static void setup_iomux_spi(void)
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{
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/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
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mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
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/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
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/* de-select SS1 of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
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/* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
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mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
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/* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
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/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
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}
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#endif
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static void power_init(void)
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{
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unsigned int val;
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unsigned int reg;
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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/* Write needed to Power Gate 2 register */
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val = pmic_reg_read(REG_POWER_MISC);
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val &= ~PWGT2SPIEN;
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pmic_reg_write(REG_POWER_MISC, val);
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/* Externally powered */
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val = pmic_reg_read(REG_CHARGE);
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val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
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pmic_reg_write(REG_CHARGE, val);
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/* power up the system first */
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pmic_reg_write(REG_POWER_MISC, PWUP);
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/* Set core voltage to 1.1V */
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val = pmic_reg_read(REG_SW_0);
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val = (val & (~0x1F)) | 0x14;
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pmic_reg_write(REG_SW_0, val);
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/* Setup VCC (SW2) to 1.25 */
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val = pmic_reg_read(REG_SW_1);
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val = (val & (~0x1F)) | 0x1A;
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pmic_reg_write(REG_SW_1, val);
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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val = pmic_reg_read(REG_SW_2);
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val = (val & (~0x1F)) | 0x1A;
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pmic_reg_write(REG_SW_2, val);
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udelay(50);
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/* Raise the core frequency to 800MHz */
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writel(0x0, &mxc_ccm->cacrr);
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/* Set switchers in Auto in NORMAL mode & STANDBY mode */
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/* Setup the switcher mode for SW1 & SW2*/
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val = pmic_reg_read(REG_SW_4);
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val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
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(SWMODE_MASK << SWMODE2_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
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pmic_reg_write(REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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val = pmic_reg_read(REG_SW_5);
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val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
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(SWMODE_MASK << SWMODE4_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
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pmic_reg_write(REG_SW_5, val);
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/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
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val = pmic_reg_read(REG_SETTING_0);
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val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
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val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
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pmic_reg_write(REG_SETTING_0, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
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val = pmic_reg_read(REG_SETTING_1);
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val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
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val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
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pmic_reg_write(REG_SETTING_1, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = VGEN3CONFIG | VCAMCONFIG;
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pmic_reg_write(REG_MODE_1, val);
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udelay(200);
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reg = readl(GPIO2_BASE_ADDR + 0x0);
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reg &= ~0x4000; /* Lower reset line */
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writel(reg, GPIO2_BASE_ADDR + 0x0);
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reg = readl(GPIO2_BASE_ADDR + 0x4);
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reg |= 0x4000; /* configure GPIO lines as output */
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writel(reg, GPIO2_BASE_ADDR + 0x4);
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/* Reset the ethernet controller over GPIO */
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writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
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VVIDEOEN | VAUDIOEN | VSDEN;
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pmic_reg_write(REG_MODE_1, val);
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udelay(500);
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reg = readl(GPIO2_BASE_ADDR + 0x0);
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reg |= 0x4000;
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writel(reg, GPIO2_BASE_ADDR + 0x0);
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_getcd(u8 *cd, struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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*cd = readl(GPIO1_BASE_ADDR) & 0x01;
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else
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*cd = readl(GPIO1_BASE_ADDR) & 0x40;
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index;
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s32 status = 0;
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
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index++) {
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switch (index) {
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case 0:
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mxc_request_iomux(MX51_PIN_SD1_CMD,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_CLK,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA0,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA1,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA2,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA3,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_GPIO1_0,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
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PAD_CTL_HYS_ENABLE);
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mxc_request_iomux(MX51_PIN_GPIO1_1,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
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PAD_CTL_HYS_ENABLE);
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break;
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case 1:
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mxc_request_iomux(MX51_PIN_SD2_CMD,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD2_CLK,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD2_DATA0,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX51_PIN_SD2_DATA1,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX51_PIN_SD2_DATA2,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX51_PIN_SD2_DATA3,
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IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_SD2_CMD,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_GPIO1_6,
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|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
|
|
PAD_CTL_HYS_ENABLE);
|
|
mxc_request_iomux(MX51_PIN_GPIO1_5,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
|
|
PAD_CTL_HYS_ENABLE);
|
|
break;
|
|
default:
|
|
printf("Warning: you configured more ESDHC controller"
|
|
"(%d) as supported by the board(2)\n",
|
|
CONFIG_SYS_FSL_ESDHC_NUM);
|
|
return status;
|
|
}
|
|
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
|
|
}
|
|
return status;
|
|
}
|
|
#endif
|
|
|
|
int board_init(void)
|
|
{
|
|
system_rev = get_cpu_rev();
|
|
|
|
gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
|
|
|
setup_iomux_uart();
|
|
setup_iomux_fec();
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef BOARD_LATE_INIT
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_MXC_SPI
|
|
setup_iomux_spi();
|
|
power_init();
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: MX51EVK ");
|
|
|
|
switch (system_rev & 0xff) {
|
|
case CHIP_REV_3_0:
|
|
puts("3.0 [");
|
|
break;
|
|
case CHIP_REV_2_5:
|
|
puts("2.5 [");
|
|
break;
|
|
case CHIP_REV_2_0:
|
|
puts("2.0 [");
|
|
break;
|
|
case CHIP_REV_1_1:
|
|
puts("1.1 [");
|
|
break;
|
|
case CHIP_REV_1_0:
|
|
default:
|
|
puts("1.0 [");
|
|
break;
|
|
}
|
|
|
|
switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
|
|
case 0x0001:
|
|
puts("POR");
|
|
break;
|
|
case 0x0009:
|
|
puts("RST");
|
|
break;
|
|
case 0x0010:
|
|
case 0x0011:
|
|
puts("WDOG");
|
|
break;
|
|
default:
|
|
puts("unknown");
|
|
}
|
|
puts("]\n");
|
|
return 0;
|
|
}
|
|
|