upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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202 lines
6.0 KiB
202 lines
6.0 KiB
/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <pci.h>
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u_long pci9054_iobase;
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#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */
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#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */
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/*-----------------------------------------------------------------------------+
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| Subroutine: pci9054_read_config_dword
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| Description: Read a PCI configuration register
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| Inputs:
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| hose PCI Controller
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| dev PCI Bus+Device+Function number
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| offset Configuration register number
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| value Address of the configuration register value
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| Return value:
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| 0 Successful
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+-----------------------------------------------------------------------------*/
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int pci9054_read_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32* value)
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{
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unsigned long conAdrVal;
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unsigned long val;
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/* generate coded value for CON_ADR register */
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conAdrVal = dev | (offset & 0xfc) | 0x80000000;
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/* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
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*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
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/* Note: *pResult comes back as -1 if machine check happened */
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val = in32r(PCI_PRIMARY_CDR);
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*value = (unsigned long) val;
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out32r(PCI_PRIMARY_CAR, 0);
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if ((*(unsigned long *)0x50000304) & 0x60000000)
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{
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/* clear pci master/target abort bits */
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*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
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}
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return 0;
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}
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/*-----------------------------------------------------------------------------+
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| Subroutine: pci9054_write_config_dword
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| Description: Write a PCI configuration register.
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| Inputs:
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| hose PCI Controller
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| dev PCI Bus+Device+Function number
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| offset Configuration register number
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| Value Configuration register value
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| Return value:
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| 0 Successful
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| Updated for pass2 errata #6. Need to disable interrupts and clear the
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| PCICFGADR reg after writing the PCICFGDATA reg.
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+-----------------------------------------------------------------------------*/
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int pci9054_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 value)
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{
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unsigned long conAdrVal;
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conAdrVal = dev | (offset & 0xfc) | 0x80000000;
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*(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
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out32r(PCI_PRIMARY_CDR, value);
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out32r(PCI_PRIMARY_CAR, 0);
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/* clear pci master/target abort bits */
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*(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
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return (0);
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}
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/*-----------------------------------------------------------------------
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*/
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#ifdef CONFIG_DASA_SIM
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static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
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struct pci_config_table *_)
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{
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unsigned int iobase;
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unsigned short status = 0;
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unsigned char timer;
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/*
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* Configure PLX PCI9054
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*/
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pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status);
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status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status);
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/* Check the latency timer for values >= 0x60.
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*/
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pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
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if (timer < 0x60)
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{
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pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
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}
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/* Set I/O base register.
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*/
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pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE);
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pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
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pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
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if (pci9054_iobase == 0xffffffff)
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{
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printf("Error: Can not set I/O base register.\n");
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return;
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}
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}
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#endif
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static struct pci_config_table pci9054_config_table[] = {
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#ifndef CONFIG_PCI_PNP
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
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pci_cfgfunc_config_device, { CFG_ETH_IOBASE,
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CFG_ETH_IOBASE,
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PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
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#ifdef CONFIG_DASA_SIM
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN),
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pci_dasa_sim_config_pci9054 },
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#endif
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#endif
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{ }
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};
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static struct pci_controller pci9054_hose = {
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config_table: pci9054_config_table,
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};
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void pci_init_board(void)
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{
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struct pci_controller *hose = &pci9054_hose;
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/*
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* Register the hose
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*/
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space */
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pci_set_region(hose->regions + 0,
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0x00000000, 0x00000000, 0x01000000,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI Memory space */
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pci_set_region(hose->regions + 1,
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0x00000000, 0xc0000000, 0x10000000,
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PCI_REGION_MEM);
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pci_set_ops(hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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pci9054_read_config_dword,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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pci9054_write_config_dword);
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hose->region_count = 2;
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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}
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