upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.8 KiB
149 lines
3.8 KiB
/*
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* U-Boot - Configuration file for BF561 Acvilon System On Module
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* For more information please go to http://www.niistt.ru/
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*/
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#ifndef __CONFIG_BF561_ACVILON_H__
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#define __CONFIG_BF561_ACVILON_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf561-0.5
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 12000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 50
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 10
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#define CONFIG_MEM_SIZE 128
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#define CONFIG_EBIU_SDRRC_VAL 0x300
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#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189
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#define CONFIG_EBIU_AMGCTL_VAL 0x4e
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#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
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#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
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/*
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* RTC Settings
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*/
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_I2C_DTT_ADDR 0x49
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/*#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3*/
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/*
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* Network Settings
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*/
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DTT
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_SMC911X 1
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#define CONFIG_SMC911X_32_BIT
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/* #define CONFIG_SMC911X_16_BIT */
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#define CONFIG_SMC911X_BASE 0x28000000
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#endif /* (CONFIG_CMD_NET) */
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#define CONFIG_HOSTNAME bf561-acvilon
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/*
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* Flash Settings
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*/
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#define CONFIG_SYS_NO_FLASH
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/*
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* I2C Settings
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*/
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#define CONFIG_HARD_I2C
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/* Use 300kHz speed by default */
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#define CONFIG_SYS_I2C_SPEED 0x00
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#define CONFIG_PCA9564_I2C
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#define CONFIG_PCA9564_BASE 0x2c000000
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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/*
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* Env Storage Settings
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*/
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SECT_SIZE (1056 * 8)
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#define CONFIG_ENV_OFFSET ((16 + 256) * 1056)
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#define CONFIG_ENV_SIZE (8 * 1056)
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/*
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* NAND Settings
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* We're using NAND_PLAT driver to make things simplier
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*/
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#define CONFIG_NAND_PLAT
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BASE 0x24000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
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#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
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#define BFIN_NAND_WRITE(addr, cmd) \
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do { \
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bfin_write8(addr, cmd); \
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SSYNC(); \
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} while (0)
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#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
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#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
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#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
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/*
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* Misc Settings
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*/
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_BAUDRATE 57600
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif /* __CONFIG_BF561_ACVILON_H__ */
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