upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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348 lines
9.4 KiB
348 lines
9.4 KiB
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <pci.h>
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#include <libfdt.h>
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* MDIO */
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{0, 1, 3, 0, 2}, /* MDIO */
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{0, 2, 1, 0, 1}, /* MDC */
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/* UCC1 - UEC (Gigabit) */
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{0, 3, 1, 0, 1}, /* TxD0 */
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{0, 4, 1, 0, 1}, /* TxD1 */
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{0, 5, 1, 0, 1}, /* TxD2 */
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{0, 6, 1, 0, 1}, /* TxD3 */
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{0, 9, 2, 0, 1}, /* RxD0 */
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{0, 10, 2, 0, 1}, /* RxD1 */
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{0, 11, 2, 0, 1}, /* RxD2 */
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{0, 12, 2, 0, 1}, /* RxD3 */
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{0, 7, 1, 0, 1}, /* TX_EN */
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{0, 8, 1, 0, 1}, /* TX_ER */
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{0, 15, 2, 0, 1}, /* RX_DV */
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{0, 0, 2, 0, 1}, /* RX_CLK */
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{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
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{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
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/* UCC2 - UEC (Gigabit) */
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{0, 17, 1, 0, 1}, /* TxD0 */
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{0, 18, 1, 0, 1}, /* TxD1 */
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{0, 19, 1, 0, 1}, /* TxD2 */
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{0, 20, 1, 0, 1}, /* TxD3 */
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{0, 23, 2, 0, 1}, /* RxD0 */
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{0, 24, 2, 0, 1}, /* RxD1 */
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{0, 25, 2, 0, 1}, /* RxD2 */
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{0, 26, 2, 0, 1}, /* RxD3 */
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{0, 21, 1, 0, 1}, /* TX_EN */
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{0, 22, 1, 0, 1}, /* TX_ER */
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{0, 29, 2, 0, 1}, /* RX_DV */
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{0, 31, 2, 0, 1}, /* RX_CLK */
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{2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */
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{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
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/* UCC7 - UEC */
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{4, 0, 1, 0, 1}, /* TxD0 */
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{4, 1, 1, 0, 1}, /* TxD1 */
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{4, 2, 1, 0, 1}, /* TxD2 */
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{4, 3, 1, 0, 1}, /* TxD3 */
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{4, 6, 2, 0, 1}, /* RxD0 */
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{4, 7, 2, 0, 1}, /* RxD1 */
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{4, 8, 2, 0, 1}, /* RxD2 */
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{4, 9, 2, 0, 1}, /* RxD3 */
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{4, 4, 1, 0, 1}, /* TX_EN */
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{4, 5, 1, 0, 1}, /* TX_ER */
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{4, 12, 2, 0, 1}, /* RX_DV */
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{4, 13, 2, 0, 1}, /* RX_ER */
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{4, 10, 2, 0, 1}, /* COL */
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{4, 11, 2, 0, 1}, /* CRS */
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{2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
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{2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
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/* UCC4 - UEC */
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{1, 14, 1, 0, 1}, /* TxD0 */
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{1, 15, 1, 0, 1}, /* TxD1 */
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{1, 16, 1, 0, 1}, /* TxD2 */
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{1, 17, 1, 0, 1}, /* TxD3 */
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{1, 20, 2, 0, 1}, /* RxD0 */
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{1, 21, 2, 0, 1}, /* RxD1 */
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{1, 22, 2, 0, 1}, /* RxD2 */
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{1, 23, 2, 0, 1}, /* RxD3 */
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{1, 18, 1, 0, 1}, /* TX_EN */
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{1, 19, 1, 0, 2}, /* TX_ER */
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{1, 26, 2, 0, 1}, /* RX_DV */
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{1, 27, 2, 0, 1}, /* RX_ER */
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{1, 24, 2, 0, 1}, /* COL */
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{1, 25, 2, 0, 1}, /* CRS */
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{2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */
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{2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */
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/* PCI1 */
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{5, 4, 2, 0, 3}, /* PCI_M66EN */
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{5, 5, 1, 0, 3}, /* PCI_INTA */
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{5, 6, 1, 0, 3}, /* PCI_RSTO */
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{5, 7, 3, 0, 3}, /* PCI_C_BE0 */
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{5, 8, 3, 0, 3}, /* PCI_C_BE1 */
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{5, 9, 3, 0, 3}, /* PCI_C_BE2 */
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{5, 10, 3, 0, 3}, /* PCI_C_BE3 */
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{5, 11, 3, 0, 3}, /* PCI_PAR */
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{5, 12, 3, 0, 3}, /* PCI_FRAME */
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{5, 13, 3, 0, 3}, /* PCI_TRDY */
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{5, 14, 3, 0, 3}, /* PCI_IRDY */
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{5, 15, 3, 0, 3}, /* PCI_STOP */
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{5, 16, 3, 0, 3}, /* PCI_DEVSEL */
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{5, 17, 0, 0, 0}, /* PCI_IDSEL */
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{5, 18, 3, 0, 3}, /* PCI_SERR */
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{5, 19, 3, 0, 3}, /* PCI_PERR */
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{5, 20, 3, 0, 3}, /* PCI_REQ0 */
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{5, 21, 2, 0, 3}, /* PCI_REQ1 */
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{5, 22, 2, 0, 3}, /* PCI_GNT2 */
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{5, 23, 3, 0, 3}, /* PCI_GNT0 */
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{5, 24, 1, 0, 3}, /* PCI_GNT1 */
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{5, 25, 1, 0, 3}, /* PCI_GNT2 */
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{5, 26, 0, 0, 0}, /* PCI_CLK0 */
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{5, 27, 0, 0, 0}, /* PCI_CLK1 */
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{5, 28, 0, 0, 0}, /* PCI_CLK2 */
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{5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
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{6, 0, 3, 0, 3}, /* PCI_AD0 */
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{6, 1, 3, 0, 3}, /* PCI_AD1 */
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{6, 2, 3, 0, 3}, /* PCI_AD2 */
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{6, 3, 3, 0, 3}, /* PCI_AD3 */
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{6, 4, 3, 0, 3}, /* PCI_AD4 */
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{6, 5, 3, 0, 3}, /* PCI_AD5 */
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{6, 6, 3, 0, 3}, /* PCI_AD6 */
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{6, 7, 3, 0, 3}, /* PCI_AD7 */
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{6, 8, 3, 0, 3}, /* PCI_AD8 */
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{6, 9, 3, 0, 3}, /* PCI_AD9 */
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{6, 10, 3, 0, 3}, /* PCI_AD10 */
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{6, 11, 3, 0, 3}, /* PCI_AD11 */
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{6, 12, 3, 0, 3}, /* PCI_AD12 */
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{6, 13, 3, 0, 3}, /* PCI_AD13 */
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{6, 14, 3, 0, 3}, /* PCI_AD14 */
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{6, 15, 3, 0, 3}, /* PCI_AD15 */
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{6, 16, 3, 0, 3}, /* PCI_AD16 */
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{6, 17, 3, 0, 3}, /* PCI_AD17 */
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{6, 18, 3, 0, 3}, /* PCI_AD18 */
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{6, 19, 3, 0, 3}, /* PCI_AD19 */
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{6, 20, 3, 0, 3}, /* PCI_AD20 */
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{6, 21, 3, 0, 3}, /* PCI_AD21 */
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{6, 22, 3, 0, 3}, /* PCI_AD22 */
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{6, 23, 3, 0, 3}, /* PCI_AD23 */
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{6, 24, 3, 0, 3}, /* PCI_AD24 */
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{6, 25, 3, 0, 3}, /* PCI_AD25 */
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{6, 26, 3, 0, 3}, /* PCI_AD26 */
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{6, 27, 3, 0, 3}, /* PCI_AD27 */
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{6, 28, 3, 0, 3}, /* PCI_AD28 */
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{6, 29, 3, 0, 3}, /* PCI_AD29 */
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{6, 30, 3, 0, 3}, /* PCI_AD30 */
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{6, 31, 3, 0, 3}, /* PCI_AD31 */
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/* NAND */
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{4, 18, 2, 0, 0}, /* NAND_RYnBY */
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/* DUART - UART2 */
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{5, 0, 1, 0, 2}, /* UART2_SOUT */
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{5, 2, 1, 0, 1}, /* UART2_RTS */
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{5, 3, 2, 0, 2}, /* UART2_SIN */
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{5, 1, 2, 0, 3}, /* UART2_CTS */
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/* UCC5 - UART3 */
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{3, 0, 1, 0, 1}, /* UART3_TX */
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{3, 4, 1, 0, 1}, /* UART3_RTS */
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{3, 6, 2, 0, 1}, /* UART3_RX */
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{3, 12, 2, 0, 0}, /* UART3_CTS */
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{3, 13, 2, 0, 0}, /* UCC5_CD */
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/* UCC6 - UART4 */
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{3, 14, 1, 0, 1}, /* UART4_TX */
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{3, 18, 1, 0, 1}, /* UART4_RTS */
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{3, 20, 2, 0, 1}, /* UART4_RX */
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{3, 26, 2, 0, 0}, /* UART4_CTS */
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{3, 27, 2, 0, 0}, /* UCC6_CD */
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/* Fujitsu MB86277 (MINT) graphics controller */
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{0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
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{1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */
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{1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */
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{2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
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/* AD7843 ADC/Touchscreen controller */
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{4, 14, 1, 0, 0}, /* SPI_nCS0 */
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{4, 28, 3, 0, 3}, /* SPI_MOSI */
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{4, 29, 3, 0, 3}, /* SPI_MISO */
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{4, 30, 3, 0, 3}, /* SPI_CLK */
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/* Freescale QUICC Engine USB Host Controller (FHCI) */
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{1, 2, 1, 0, 3}, /* USBOE */
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{1, 3, 1, 0, 3}, /* USBTP */
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{1, 8, 1, 0, 1}, /* USBTN */
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{1, 9, 2, 1, 3}, /* USBRP */
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{1, 10, 2, 0, 3}, /* USBRXD */
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{1, 11, 2, 1, 3}, /* USBRN */
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{2, 20, 2, 0, 1}, /* CLK21 */
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{4, 20, 1, 0, 0}, /* SPEED */
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{4, 21, 1, 0, 0}, /* SUSPND */
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/* END of table */
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{0, 0, 0, 0, QE_IOP_TAB_END},
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};
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int board_early_init_r(void)
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{
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void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
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u32 val;
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/*
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* Because of errata in the UCCs, we have to write to the reserved
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* registers to slow the clocks down.
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*/
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val = in_be32(reg);
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/* UCC1 */
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val |= 0x00003000;
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/* UCC2 */
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val |= 0x0c000000;
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out_be32(reg, val);
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return 0;
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}
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1)
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return -1;
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}
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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phys_size_t initdram(int board_type)
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{
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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msize = fixed_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize DDR ECC byte
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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int checkboard(void)
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{
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puts("Board: Freescale/Logic MPC8360ERDK\n");
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return 0;
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}
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static struct pci_region pci_regions[] = {
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{
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.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
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.size = CONFIG_SYS_PCI1_MEM_SIZE,
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.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
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},
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{
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.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
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.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
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.size = CONFIG_SYS_PCI1_MMIO_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCI1_IO_BASE,
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.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
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.size = CONFIG_SYS_PCI1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions, };
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#if defined(CONFIG_PCI_33M)
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clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
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OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
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printf("PCI clock is 33MHz\n");
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#else
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clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
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printf("PCI clock is 66MHz\n");
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#endif
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udelay(2000);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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ft_pci_setup(blob, bd);
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}
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#endif
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