upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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883 lines
21 KiB
883 lines
21 KiB
/*
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* (C) Copyright 2003-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2004-2006
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <console.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <libfdt.h>
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#include <netdev.h>
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#include <video.h>
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#ifdef CONFIG_VIDEO_SM501
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#include <sm501.h>
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#endif
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#if defined(CONFIG_MPC5200_DDR)
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#include "mt46v16m16-75.h"
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#else
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#include "mt48lc16m16a2-75.h"
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#endif
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#ifdef CONFIG_OF_LIBFDT
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#include <fdt_support.h>
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#endif /* CONFIG_OF_LIBFDT */
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_PS2MULT
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void ps2mult_early_init(void);
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#endif
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
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defined(CONFIG_VIDEO)
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/*
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* EDID block has been generated using Phoenix EDID Designer 1.3.
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* This tool creates a text file containing:
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*
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* EDID BYTES:
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*
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* 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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* ------------------------------------------------
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* 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
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* 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
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* 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
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* 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
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* 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
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* 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
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* 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
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* 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
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*
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* Then this data has been manually converted to the char
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* array below.
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*/
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static unsigned char edid_buf[128] = {
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0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
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0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
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};
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#endif
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
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hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
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hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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#endif
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
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hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
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hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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phys_size_t initdram (int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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uint svr, pvr;
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#ifndef CONFIG_SYS_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
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__builtin_ffs(dramsize >> 20) - 1;
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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}
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/* let SDRAM CS1 start right after CS0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
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/* find RAM size using SDRAM CS1 only */
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if (!dramsize)
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sdram_start(0);
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test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
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if (!dramsize) {
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sdram_start(1);
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test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
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}
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if (test1 > test2) {
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sdram_start(0);
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dramsize2 = test1;
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} else {
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dramsize2 = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize2 < (1 << 20)) {
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dramsize2 = 0;
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}
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/* set SDRAM CS1 size according to the amount of RAM found */
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if (dramsize2 > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
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| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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}
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
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if (dramsize2 >= 0x13) {
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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} else {
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dramsize2 = 0;
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}
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#endif /* CONFIG_SYS_RAMBOOT */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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svr = get_svr();
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pvr = get_pvr();
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if ((SVR_MJREV(svr) >= 2) &&
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(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
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*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
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__asm__ volatile ("sync");
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}
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#if defined(CONFIG_TQM5200_B)
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return dramsize + dramsize2;
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#else
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return dramsize;
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#endif /* CONFIG_TQM5200_B */
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}
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int checkboard (void)
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{
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#if defined(CONFIG_TQM5200S)
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# define MODULE_NAME "TQM5200S"
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#else
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# define MODULE_NAME "TQM5200"
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#endif
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#if defined(CONFIG_STK52XX)
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# define CARRIER_NAME "STK52xx"
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#elif defined(CONFIG_CAM5200)
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# define CARRIER_NAME "CAM5200"
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#elif defined(CONFIG_FO300)
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# define CARRIER_NAME "FO300"
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#elif defined(CONFIG_CHARON)
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# define CARRIER_NAME "CHARON"
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#else
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# error "UNKNOWN"
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#endif
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puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
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" on a " CARRIER_NAME " carrier board\n");
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return 0;
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}
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#undef MODULE_NAME
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#undef CARRIER_NAME
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void flash_preinit(void)
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{
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
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#if defined (CONFIG_MINIFAP)
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#define SM501_POWER_MODE0_GATE 0x00000040UL
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#define SM501_POWER_MODE1_GATE 0x00000048UL
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#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
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#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
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#define SM501_GPIO_DATA_HIGH 0x00010004UL
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#define SM501_GPIO_51 0x00080000UL
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#endif /* CONFIG MINIFAP */
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void init_ide_reset (void)
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{
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debug ("init_ide_reset\n");
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#if defined (CONFIG_MINIFAP)
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/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
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/* enable GPIO control (in both power modes) */
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*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
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POWER_MODE_GATE_GPIO_PWM_I2C;
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*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
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POWER_MODE_GATE_GPIO_PWM_I2C;
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/* configure GPIO51 as output */
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*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
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SM501_GPIO_51;
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#else
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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/* by default the ATA reset is de-asserted */
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
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#endif
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}
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void ide_set_reset (int idereset)
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{
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debug ("ide_reset(%d)\n", idereset);
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#if defined (CONFIG_MINIFAP)
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if (idereset) {
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*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
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~SM501_GPIO_51;
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} else {
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*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
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SM501_GPIO_51;
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}
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#else
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
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} else {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
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}
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#endif
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}
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#endif
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#ifdef CONFIG_POST
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/*
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* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
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* is left open, no keypress is detected.
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*/
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int post_hotkeys_pressed(void)
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{
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#ifdef CONFIG_STK52XX
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struct mpc5xxx_gpio *gpio;
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gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
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/*
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* Configure PSC6_0 through PSC6_3 as GPIO.
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*/
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gpio->port_config &= ~(0x00700000);
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/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
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gpio->simple_gpioe |= 0x20000000;
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/* Configure GPIO_IRDA_1 as input */
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gpio->simple_ddr &= ~(0x20000000);
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return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
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#else
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return 0;
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#endif
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_R
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int board_early_init_r (void)
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{
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extern int usb_cpu_init(void);
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#ifdef CONFIG_PS2MULT
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ps2mult_early_init();
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#endif /* CONFIG_PS2MULT */
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#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
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/* Low level USB init, required for proper kernel operation */
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usb_cpu_init();
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#endif
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return (0);
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}
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#endif
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#ifdef CONFIG_FO300
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int silent_boot (void)
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{
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vu_long timer3_status;
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/* Configure GPT3 as GPIO input */
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*(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
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/* Read in TIMER_3 pin status */
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timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
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#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
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/* Force silent console mode if S1 switch
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* is in closed position (TIMER_3 pin status is LOW). */
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if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
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return 1;
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#else
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/* Force silent console mode if S1 switch
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* is in open position (TIMER_3 pin status is HIGH). */
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if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
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return 1;
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#endif
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return 0;
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}
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int board_early_init_f (void)
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{
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if (silent_boot())
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gd->flags |= GD_FLG_SILENT;
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return 0;
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}
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#endif /* CONFIG_FO300 */
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#if defined(CONFIG_CHARON)
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#include <i2c.h>
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#include <asm/io.h>
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/* The TFP410 registers */
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#define TFP410_REG_VEN_ID_L 0x00
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#define TFP410_REG_VEN_ID_H 0x01
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#define TFP410_REG_DEV_ID_L 0x02
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#define TFP410_REG_DEV_ID_H 0x03
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#define TFP410_REG_REV_ID 0x04
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#define TFP410_REG_CTL_1_MODE 0x08
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#define TFP410_REG_CTL_2_MODE 0x09
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#define TFP410_REG_CTL_3_MODE 0x0A
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#define TFP410_REG_CFG 0x0B
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#define TFP410_REG_DE_DLY 0x32
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#define TFP410_REG_DE_CTL 0x33
|
|
#define TFP410_REG_DE_TOP 0x34
|
|
#define TFP410_REG_DE_CNT_L 0x36
|
|
#define TFP410_REG_DE_CNT_H 0x37
|
|
#define TFP410_REG_DE_LIN_L 0x38
|
|
#define TFP410_REG_DE_LIN_H 0x39
|
|
|
|
#define TFP410_REG_H_RES_L 0x3A
|
|
#define TFP410_REG_H_RES_H 0x3B
|
|
#define TFP410_REG_V_RES_L 0x3C
|
|
#define TFP410_REG_V_RES_H 0x3D
|
|
|
|
static int tfp410_read_reg(int reg, uchar *buf)
|
|
{
|
|
if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
|
|
puts ("Error reading the chip.\n");
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int tfp410_write_reg(int reg, uchar buf)
|
|
{
|
|
if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
|
|
puts ("Error writing the chip.\n");
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
typedef struct _tfp410_config {
|
|
int reg;
|
|
uchar val;
|
|
}TFP410_CONFIG;
|
|
|
|
static TFP410_CONFIG tfp410_configtbl[] = {
|
|
{TFP410_REG_CTL_1_MODE, 0x37},
|
|
{TFP410_REG_CTL_2_MODE, 0x20},
|
|
{TFP410_REG_CTL_3_MODE, 0x80},
|
|
{TFP410_REG_DE_DLY, 0x90},
|
|
{TFP410_REG_DE_CTL, 0x00},
|
|
{TFP410_REG_DE_TOP, 0x23},
|
|
{TFP410_REG_DE_CNT_H, 0x02},
|
|
{TFP410_REG_DE_CNT_L, 0x80},
|
|
{TFP410_REG_DE_LIN_H, 0x01},
|
|
{TFP410_REG_DE_LIN_L, 0xe0},
|
|
{-1, 0},
|
|
};
|
|
|
|
static int charon_last_stage_init(void)
|
|
{
|
|
volatile struct mpc5xxx_lpb *lpb =
|
|
(struct mpc5xxx_lpb *) MPC5XXX_LPB;
|
|
int oldbus = i2c_get_bus_num();
|
|
uchar buf;
|
|
int i = 0;
|
|
|
|
i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
|
|
|
|
/* check version */
|
|
if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
|
|
return -1;
|
|
if (!(buf & 0x04))
|
|
return -1;
|
|
if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
|
|
return -1;
|
|
if (!(buf & 0x10))
|
|
return -1;
|
|
/* OK, now init the chip */
|
|
while (tfp410_configtbl[i].reg != -1) {
|
|
int ret;
|
|
|
|
ret = tfp410_write_reg(tfp410_configtbl[i].reg,
|
|
tfp410_configtbl[i].val);
|
|
if (ret != 0)
|
|
return -1;
|
|
i++;
|
|
}
|
|
printf("TFP410 initialized.\n");
|
|
i2c_set_bus_num(oldbus);
|
|
|
|
/* set deadcycle for cs3 to 0 */
|
|
setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int last_stage_init (void)
|
|
{
|
|
/*
|
|
* auto scan for really existing devices and re-set chip select
|
|
* configuration.
|
|
*/
|
|
u16 save, tmp;
|
|
int restore;
|
|
|
|
/*
|
|
* Check for SRAM and SRAM size
|
|
*/
|
|
|
|
/* save original SRAM content */
|
|
save = *(volatile u16 *)CONFIG_SYS_CS2_START;
|
|
restore = 1;
|
|
|
|
/* write test pattern to SRAM */
|
|
*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
|
|
__asm__ volatile ("sync");
|
|
/*
|
|
* Put a different pattern on the data lines: otherwise they may float
|
|
* long enough to read back what we wrote.
|
|
*/
|
|
tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
|
|
if (tmp == 0xA5A5)
|
|
puts ("!! possible error in SRAM detection\n");
|
|
|
|
if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
|
|
/* no SRAM at all, disable cs */
|
|
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
|
|
*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
|
|
*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
|
|
restore = 0;
|
|
__asm__ volatile ("sync");
|
|
} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
|
|
/* make sure that we access a mirrored address */
|
|
*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
|
|
__asm__ volatile ("sync");
|
|
if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
|
|
/* SRAM size = 512 kByte */
|
|
*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
|
|
0x80000);
|
|
__asm__ volatile ("sync");
|
|
puts ("SRAM: 512 kB\n");
|
|
}
|
|
else
|
|
puts ("!! possible error in SRAM detection\n");
|
|
} else {
|
|
puts ("SRAM: 1 MB\n");
|
|
}
|
|
/* restore origianl SRAM content */
|
|
if (restore) {
|
|
*(volatile u16 *)CONFIG_SYS_CS2_START = save;
|
|
__asm__ volatile ("sync");
|
|
}
|
|
|
|
#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
|
|
/*
|
|
* Check for Grafic Controller
|
|
*/
|
|
|
|
/* save origianl FB content */
|
|
save = *(volatile u16 *)CONFIG_SYS_CS1_START;
|
|
restore = 1;
|
|
|
|
/* write test pattern to FB memory */
|
|
*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
|
|
__asm__ volatile ("sync");
|
|
/*
|
|
* Put a different pattern on the data lines: otherwise they may float
|
|
* long enough to read back what we wrote.
|
|
*/
|
|
tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
|
|
if (tmp == 0xA5A5)
|
|
puts ("!! possible error in grafic controller detection\n");
|
|
|
|
if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
|
|
/* no grafic controller at all, disable cs */
|
|
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
|
|
*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
|
|
*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
|
|
restore = 0;
|
|
__asm__ volatile ("sync");
|
|
} else {
|
|
puts ("VGA: SMI501 (Voyager) with 8 MB\n");
|
|
}
|
|
/* restore origianl FB content */
|
|
if (restore) {
|
|
*(volatile u16 *)CONFIG_SYS_CS1_START = save;
|
|
__asm__ volatile ("sync");
|
|
}
|
|
|
|
#ifdef CONFIG_FO300
|
|
if (silent_boot()) {
|
|
setenv("bootdelay", "0");
|
|
disable_ctrlc(1);
|
|
}
|
|
#endif
|
|
#endif /* !CONFIG_TQM5200S */
|
|
|
|
#if defined(CONFIG_CHARON)
|
|
charon_last_stage_init();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_VIDEO_SM501
|
|
|
|
#ifdef CONFIG_FO300
|
|
#define DISPLAY_WIDTH 800
|
|
#else
|
|
#define DISPLAY_WIDTH 640
|
|
#endif
|
|
#define DISPLAY_HEIGHT 480
|
|
|
|
#ifdef CONFIG_VIDEO_SM501_8BPP
|
|
#error CONFIG_VIDEO_SM501_8BPP not supported.
|
|
#endif /* CONFIG_VIDEO_SM501_8BPP */
|
|
|
|
#ifdef CONFIG_VIDEO_SM501_16BPP
|
|
#error CONFIG_VIDEO_SM501_16BPP not supported.
|
|
#endif /* CONFIG_VIDEO_SM501_16BPP */
|
|
#ifdef CONFIG_VIDEO_SM501_32BPP
|
|
static const SMI_REGS init_regs [] =
|
|
{
|
|
#if 0 /* CRT only */
|
|
{0x00004, 0x0},
|
|
{0x00048, 0x00021807},
|
|
{0x0004C, 0x10090a01},
|
|
{0x00054, 0x1},
|
|
{0x00040, 0x00021807},
|
|
{0x00044, 0x10090a01},
|
|
{0x00054, 0x0},
|
|
{0x80200, 0x00010000},
|
|
{0x80204, 0x0},
|
|
{0x80208, 0x0A000A00},
|
|
{0x8020C, 0x02fa027f},
|
|
{0x80210, 0x004a028b},
|
|
{0x80214, 0x020c01df},
|
|
{0x80218, 0x000201e9},
|
|
{0x80200, 0x00013306},
|
|
#else /* panel + CRT */
|
|
#ifdef CONFIG_FO300
|
|
{0x00004, 0x0},
|
|
{0x00048, 0x00021807},
|
|
{0x0004C, 0x301a0a01},
|
|
{0x00054, 0x1},
|
|
{0x00040, 0x00021807},
|
|
{0x00044, 0x091a0a01},
|
|
{0x00054, 0x0},
|
|
{0x80000, 0x0f013106},
|
|
{0x80004, 0xc428bb17},
|
|
{0x8000C, 0x00000000},
|
|
{0x80010, 0x0C800C80},
|
|
{0x80014, 0x03200000},
|
|
{0x80018, 0x01e00000},
|
|
{0x8001C, 0x00000000},
|
|
{0x80020, 0x01e00320},
|
|
{0x80024, 0x042a031f},
|
|
{0x80028, 0x0086034a},
|
|
{0x8002C, 0x020c01df},
|
|
{0x80030, 0x000201ea},
|
|
{0x80200, 0x00010000},
|
|
#else
|
|
{0x00004, 0x0},
|
|
{0x00048, 0x00021807},
|
|
{0x0004C, 0x091a0a01},
|
|
{0x00054, 0x1},
|
|
{0x00040, 0x00021807},
|
|
{0x00044, 0x091a0a01},
|
|
{0x00054, 0x0},
|
|
{0x80000, 0x0f013106},
|
|
{0x80004, 0xc428bb17},
|
|
{0x8000C, 0x00000000},
|
|
{0x80010, 0x0a000a00},
|
|
{0x80014, 0x02800000},
|
|
{0x80018, 0x01e00000},
|
|
{0x8001C, 0x00000000},
|
|
{0x80020, 0x01e00280},
|
|
{0x80024, 0x02fa027f},
|
|
{0x80028, 0x004a028b},
|
|
{0x8002C, 0x020c01df},
|
|
{0x80030, 0x000201e9},
|
|
{0x80200, 0x00010000},
|
|
#endif /* #ifdef CONFIG_FO300 */
|
|
#endif
|
|
{0, 0}
|
|
};
|
|
#endif /* CONFIG_VIDEO_SM501_32BPP */
|
|
|
|
#ifdef CONFIG_CONSOLE_EXTRA_INFO
|
|
/*
|
|
* Return text to be printed besides the logo.
|
|
*/
|
|
void video_get_info_str (int line_number, char *info)
|
|
{
|
|
if (line_number == 1) {
|
|
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
|
|
#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
|
|
defined(CONFIG_STK52XX)
|
|
} else if (line_number == 2) {
|
|
#if defined (CONFIG_CHARON)
|
|
strcpy (info, " on a CHARON carrier board");
|
|
#endif
|
|
#if defined (CONFIG_STK52XX)
|
|
strcpy (info, " on a STK52xx carrier board");
|
|
#endif
|
|
#if defined (CONFIG_FO300)
|
|
strcpy (info, " on a FO300 carrier board");
|
|
#endif
|
|
#endif
|
|
}
|
|
else {
|
|
info [0] = '\0';
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Returns SM501 register base address. First thing called in the
|
|
* driver. Checks if SM501 is physically present.
|
|
*/
|
|
unsigned int board_video_init (void)
|
|
{
|
|
u16 save, tmp;
|
|
int restore, ret;
|
|
|
|
/*
|
|
* Check for Grafic Controller
|
|
*/
|
|
|
|
/* save origianl FB content */
|
|
save = *(volatile u16 *)CONFIG_SYS_CS1_START;
|
|
restore = 1;
|
|
|
|
/* write test pattern to FB memory */
|
|
*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
|
|
__asm__ volatile ("sync");
|
|
/*
|
|
* Put a different pattern on the data lines: otherwise they may float
|
|
* long enough to read back what we wrote.
|
|
*/
|
|
tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
|
|
if (tmp == 0xA5A5)
|
|
puts ("!! possible error in grafic controller detection\n");
|
|
|
|
if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
|
|
/* no grafic controller found */
|
|
restore = 0;
|
|
ret = 0;
|
|
} else {
|
|
ret = SM501_MMIO_BASE;
|
|
}
|
|
|
|
if (restore) {
|
|
*(volatile u16 *)CONFIG_SYS_CS1_START = save;
|
|
__asm__ volatile ("sync");
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Returns SM501 framebuffer address
|
|
*/
|
|
unsigned int board_video_get_fb (void)
|
|
{
|
|
return SM501_FB_BASE;
|
|
}
|
|
|
|
/*
|
|
* Called after initializing the SM501 and before clearing the screen.
|
|
*/
|
|
void board_validate_screen (unsigned int base)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Return a pointer to the initialization sequence.
|
|
*/
|
|
const SMI_REGS *board_get_regs (void)
|
|
{
|
|
return init_regs;
|
|
}
|
|
|
|
int board_get_width (void)
|
|
{
|
|
return DISPLAY_WIDTH;
|
|
}
|
|
|
|
int board_get_height (void)
|
|
{
|
|
return DISPLAY_HEIGHT;
|
|
}
|
|
|
|
#endif /* CONFIG_VIDEO_SM501 */
|
|
|
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
ft_cpu_setup(blob, bd);
|
|
#if defined(CONFIG_VIDEO)
|
|
fdt_add_edid(blob, "smi,sm501", edid_buf);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
|
|
|
#if defined(CONFIG_RESET_PHY_R)
|
|
#include <miiphy.h>
|
|
|
|
void reset_phy(void)
|
|
{
|
|
/* init Micrel KSZ8993 PHY */
|
|
miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
|
|
}
|
|
#endif
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
cpu_eth_init(bis); /* Built in FEC comes first */
|
|
return pci_eth_init(bis);
|
|
}
|
|
|