upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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252 lines
7.1 KiB
252 lines
7.1 KiB
/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2003 Motorola Inc.
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* Xianghua Xiao (x.xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Change log:
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*
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* 20050101: Eran Liberty (liberty@freescale.com)
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* Initial file creating (porting from 85XX & 8260)
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*/
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/*
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* PCI Configuration space access support for MPC85xx PCI Bridge
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*/
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <common.h>
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#include <pci.h>
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#ifdef CONFIG_MPC8349ADS
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#include <asm/i2c.h>
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#endif
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#if defined(CONFIG_PCI)
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void
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pci_mpc83xx_init(volatile struct pci_controller *hose)
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{
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volatile immap_t * immr;
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volatile clk8349_t * clk;
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volatile law8349_t * pci_law;
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volatile pot8349_t * pci_pot;
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volatile pcictrl8349_t * pci_ctrl;
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volatile pciconf8349_t * pci_conf;
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u8 val8,tmp8,ret;
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u16 reg16,tmp16;
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u32 val32,tmp32;
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immr = (immap_t *)CFG_IMMRBAR;
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clk = (clk8349_t *)&immr->clk;
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pci_law = immr->sysconf.pcilaw;
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pci_pot = immr->ios.pot;
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pci_ctrl = immr->pci_ctrl;
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pci_conf = immr->pci_conf;
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/*
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* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
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*/
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val32 = clk->occr;
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udelay(2000);
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clk->occr = 0xff000000;
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udelay(2000);
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
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pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
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/*
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* Configure PCI Outbound Translation Windows
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*/
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pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
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/* mapped to PCI1 IO space 0x0 to local 0xe2000000 */
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pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
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pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
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/* mapped to PCI2 IO space 0x0 to local 0xe3000000 */
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pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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pci_ctrl[0].pitar1 = 0x0;
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pci_ctrl[0].pibar1 = 0x0;
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pci_ctrl[0].piebar1 = 0x0;
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pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
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pci_ctrl[1].pitar1 = 0x0;
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pci_ctrl[1].pibar1 = 0x0;
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pci_ctrl[1].piebar1 = 0x0;
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pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
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/*
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* Assign PIB PMC slot to desired PCI bus
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*/
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#ifdef CONFIG_MPC8349ADS
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mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
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i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
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#endif
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val8 = 0;
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ret = i2c_write(0x23,0x6,1,&val8,1);
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ret = i2c_write(0x23,0x7,1,&val8,1);
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val8 = 0xff;
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ret = i2c_write(0x23,0x2,1,&val8,1);
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ret = i2c_write(0x23,0x3,1,&val8,1);
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val8 = 0;
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ret = i2c_write(0x26,0x6,1,&val8,1);
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val8 = 0x34;
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ret = i2c_write(0x26,0x7,1,&val8,1);
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#if defined(PCI_64BIT)
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val8 = 0xf4; /* PMC2<->PCI1 64bit */
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#elif defined(PCI_ALL_PCI1)
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val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
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#elif defined(PCI_ONE_PCI1)
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val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
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#elif defined(PCI_TWO_PCI1)
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val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
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#else
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val8 = 0xf5;
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#endif
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ret = i2c_write(0x26,0x2,1,&val8,1);
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val8 = 0xff;
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ret = i2c_write(0x26,0x3,1,&val8,1);
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val8 = 0;
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ret = i2c_write(0x27,0x6,1,&val8,1);
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ret = i2c_write(0x27,0x7,1,&val8,1);
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val8 = 0xff;
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ret = i2c_write(0x27,0x2,1,&val8,1);
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val8 = 0xef;
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ret = i2c_write(0x27,0x3,1,&val8,1);
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asm("eieio");
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/*
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* Release PCI RST Output signal
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*/
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udelay(2000);
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pci_ctrl[0].gcr = 1;
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#ifndef PCI_64BIT
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pci_ctrl[1].gcr = 1;
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#endif
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udelay(2000);
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hose[0].first_busno = 0;
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hose[0].last_busno = 0xff;
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pci_set_region(hose[0].regions + 0,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose[0].regions + 1,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose[0].region_count = 2;
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pci_setup_indirect(&hose[0],
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(CFG_IMMRBAR+0x8300),
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(CFG_IMMRBAR+0x8304));
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#define PCI_CLASS_BRIDGE 0x06
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reg16 = 0xff;
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tmp32 = 0xffff;
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pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
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pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
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#ifndef PCI_64BIT
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hose[1].first_busno = 0;
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hose[1].last_busno = 0xff;
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pci_set_region(hose[1].regions + 0,
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CFG_PCI2_MEM_BASE,
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CFG_PCI2_MEM_PHYS,
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CFG_PCI2_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose[1].regions + 1,
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CFG_PCI2_IO_BASE,
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CFG_PCI2_IO_PHYS,
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CFG_PCI2_IO_SIZE,
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PCI_REGION_IO);
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hose[1].region_count = 2;
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pci_setup_indirect(&hose[1],
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(CFG_IMMRBAR+0x8380),
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(CFG_IMMRBAR+0x8384));
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pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
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pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
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#endif
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#if defined(PCI_64BIT)
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printf("PCI1 64bit on PMC2\n");
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#elif defined(PCI_ALL_PCI1)
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printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
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#elif defined(PCI_ONE_PCI1)
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printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
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#else
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printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
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#endif
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#if 1
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/*
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* Hose scan.
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*/
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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#endif
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}
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#endif /* CONFIG_PCI */
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