upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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485 lines
10 KiB
485 lines
10 KiB
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_HARD_I2C
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#include <mpc5xxx.h>
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#include <i2c.h>
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#if !defined(CONFIG_I2C_MULTI_BUS)
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#if (CONFIG_SYS_I2C_MODULE == 2)
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#define I2C_BASE MPC5XXX_I2C2
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#elif (CONFIG_SYS_I2C_MODULE == 1)
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#define I2C_BASE MPC5XXX_I2C1
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#else
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#error CONFIG_SYS_I2C_MODULE is not properly configured
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#endif
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#else
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static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
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CONFIG_SYS_SPD_BUS_NUM;
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static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED,
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CONFIG_SYS_I2C_SPEED};
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static const unsigned long i2c_dev[2] = {
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MPC5XXX_I2C1,
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MPC5XXX_I2C2,
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};
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#define I2C_BASE ((struct mpc5xxx_i2c *)i2c_dev[i2c_bus_num])
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#endif
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#define I2C_TIMEOUT 6667
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#define I2C_RETRIES 3
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struct mpc5xxx_i2c_tap {
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int scl2tap;
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int tap2tap;
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};
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static int mpc_reg_in (volatile u32 *reg);
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static void mpc_reg_out (volatile u32 *reg, int val, int mask);
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static int wait_for_bb (void);
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static int wait_for_pin (int *status);
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static int do_address (uchar chip, char rdwr_flag);
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static int send_bytes (uchar chip, char *buf, int len);
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static int receive_bytes (uchar chip, char *buf, int len);
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static int mpc_get_fdr (int);
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static int mpc_reg_in(volatile u32 *reg)
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{
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int ret = *reg >> 24;
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__asm__ __volatile__ ("eieio");
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return ret;
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}
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static void mpc_reg_out(volatile u32 *reg, int val, int mask)
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{
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int tmp;
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if (!mask) {
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*reg = val << 24;
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} else {
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tmp = mpc_reg_in(reg);
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*reg = ((tmp & ~mask) | (val & mask)) << 24;
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}
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__asm__ __volatile__ ("eieio");
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return;
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}
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static int wait_for_bb(void)
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{
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int timeout = I2C_TIMEOUT;
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int status;
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status = mpc_reg_in(®s->msr);
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while (timeout-- && (status & I2C_BB)) {
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#if 1
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volatile int temp;
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mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
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temp = mpc_reg_in(®s->mdr);
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mpc_reg_out(®s->mcr, 0, I2C_STA);
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mpc_reg_out(®s->mcr, 0, 0);
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mpc_reg_out(®s->mcr, I2C_EN, 0);
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#endif
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udelay(15);
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status = mpc_reg_in(®s->msr);
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}
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return (status & I2C_BB);
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}
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static int wait_for_pin(int *status)
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{
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int timeout = I2C_TIMEOUT;
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*status = mpc_reg_in(®s->msr);
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while (timeout-- && !(*status & I2C_IF)) {
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udelay(15);
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*status = mpc_reg_in(®s->msr);
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}
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if (!(*status & I2C_IF)) {
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return -1;
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}
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mpc_reg_out(®s->msr, 0, I2C_IF);
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return 0;
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}
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static int do_address(uchar chip, char rdwr_flag)
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{
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int status;
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chip <<= 1;
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if (rdwr_flag) {
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chip |= 1;
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}
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mpc_reg_out(®s->mcr, I2C_TX, I2C_TX);
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mpc_reg_out(®s->mdr, chip, 0);
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if (wait_for_pin(&status)) {
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return -2;
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}
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if (status & I2C_RXAK) {
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return -3;
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}
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return 0;
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}
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static int send_bytes(uchar chip, char *buf, int len)
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{
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int wrcount;
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int status;
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for (wrcount = 0; wrcount < len; ++wrcount) {
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mpc_reg_out(®s->mdr, buf[wrcount], 0);
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if (wait_for_pin(&status)) {
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break;
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}
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if (status & I2C_RXAK) {
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break;
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}
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}
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return !(wrcount == len);
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}
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static int receive_bytes(uchar chip, char *buf, int len)
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{
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int dummy = 1;
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int rdcount = 0;
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int status;
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int i;
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mpc_reg_out(®s->mcr, 0, I2C_TX);
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for (i = 0; i < len; ++i) {
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buf[rdcount] = mpc_reg_in(®s->mdr);
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if (dummy) {
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dummy = 0;
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} else {
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rdcount++;
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}
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if (wait_for_pin(&status)) {
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return -4;
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}
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}
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mpc_reg_out(®s->mcr, I2C_TXAK, I2C_TXAK);
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buf[rdcount++] = mpc_reg_in(®s->mdr);
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if (wait_for_pin(&status)) {
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return -5;
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}
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mpc_reg_out(®s->mcr, 0, I2C_TXAK);
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return 0;
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}
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#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
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#define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3))
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#define FDR432(x) (u8) ((x & 0x1C) >> 2)
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/*
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* Reset any i2c devices that may have been interrupted during a system reset.
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* Normally this would be accomplished by clocking the line until SCL and SDA
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* are released and then sending a start condtiion (From an Atmel datasheet).
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* There is no direct access to the i2c pins so instead create start commands
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* through the i2c interface. Send a start command then delay for the SDA Hold
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* time, repeat this by disabling/enabling the bus a total of 9 times.
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*/
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static void send_reset(void)
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{
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int i;
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u32 delay;
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u8 fdr;
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int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2};
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struct mpc5xxx_i2c_tap scltap[] = {
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{4, 1},
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{4, 2},
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{6, 4},
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{6, 8},
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{14, 16},
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{30, 32},
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{62, 64},
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{126, 128}
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};
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fdr = (u8)mpc_reg_in(®s->mfdr);
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delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \
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scltap[FDR432(fdr)].tap2tap) + 3;
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for (i = 0; i < 9; i++) {
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mpc_reg_out(®s->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK);
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udelay(delay);
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mpc_reg_out(®s->mcr, 0, I2C_INIT_MASK);
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udelay(delay);
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}
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mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
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}
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#endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */
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/**************** I2C API ****************/
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void i2c_init(int speed, int saddr)
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{
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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mpc_reg_out(®s->mcr, 0, 0);
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mpc_reg_out(®s->madr, saddr << 1, 0);
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/* Set clock
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*/
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mpc_reg_out(®s->mfdr, mpc_get_fdr(speed), 0);
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/* Enable module
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*/
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mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
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mpc_reg_out(®s->msr, 0, I2C_IF);
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#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
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send_reset();
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#endif
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return;
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}
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static int mpc_get_fdr(int speed)
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{
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static int fdr = -1;
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if (fdr == -1) {
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ulong best_speed = 0;
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ulong divider;
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ulong ipb, scl;
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ulong bestmatch = 0xffffffffUL;
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int best_i = 0, best_j = 0, i, j;
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int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8};
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struct mpc5xxx_i2c_tap scltap[] = {
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{4, 1},
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{4, 2},
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{6, 4},
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{6, 8},
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{14, 16},
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{30, 32},
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{62, 64},
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{126, 128}
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};
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ipb = gd->ipb_clk;
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for (i = 7; i >= 0; i--) {
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for (j = 7; j >= 0; j--) {
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scl = 2 * (scltap[j].scl2tap +
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(SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
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if (ipb <= speed*scl) {
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if ((speed*scl - ipb) < bestmatch) {
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bestmatch = speed*scl - ipb;
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best_i = i;
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best_j = j;
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best_speed = ipb/scl;
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}
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}
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}
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}
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divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
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if (gd->flags & GD_FLG_RELOC) {
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fdr = divider;
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} else {
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if (gd->have_console)
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printf("%ld kHz, ", best_speed / 1000);
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return divider;
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}
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}
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return fdr;
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}
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int i2c_probe(uchar chip)
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{
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int i;
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for (i = 0; i < I2C_RETRIES; i++) {
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mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
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if (! do_address(chip, 0)) {
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mpc_reg_out(®s->mcr, 0, I2C_STA);
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udelay(500);
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break;
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}
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mpc_reg_out(®s->mcr, 0, I2C_STA);
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udelay(500);
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}
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return (i == I2C_RETRIES);
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}
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int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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char xaddr[4];
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struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int ret = -1;
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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if (wait_for_bb()) {
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if (gd->have_console)
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printf("i2c_read: bus is busy\n");
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goto Done;
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}
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mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
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if (do_address(chip, 0)) {
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if (gd->have_console)
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printf("i2c_read: failed to address chip\n");
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goto Done;
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}
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if (send_bytes(chip, &xaddr[4-alen], alen)) {
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if (gd->have_console)
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printf("i2c_read: send_bytes failed\n");
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goto Done;
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}
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mpc_reg_out(®s->mcr, I2C_RSTA, I2C_RSTA);
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if (do_address(chip, 1)) {
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if (gd->have_console)
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printf("i2c_read: failed to address chip\n");
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goto Done;
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}
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if (receive_bytes(chip, (char *)buf, len)) {
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if (gd->have_console)
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printf("i2c_read: receive_bytes failed\n");
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goto Done;
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}
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ret = 0;
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Done:
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mpc_reg_out(®s->mcr, 0, I2C_STA);
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return ret;
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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char xaddr[4];
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struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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int ret = -1;
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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if (wait_for_bb()) {
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if (gd->have_console)
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printf("i2c_write: bus is busy\n");
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goto Done;
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}
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mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
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if (do_address(chip, 0)) {
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if (gd->have_console)
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printf("i2c_write: failed to address chip\n");
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goto Done;
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}
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if (send_bytes(chip, &xaddr[4-alen], alen)) {
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if (gd->have_console)
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printf("i2c_write: send_bytes failed\n");
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goto Done;
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}
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if (send_bytes(chip, (char *)buf, len)) {
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if (gd->have_console)
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printf("i2c_write: send_bytes failed\n");
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goto Done;
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}
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ret = 0;
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Done:
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mpc_reg_out(®s->mcr, 0, I2C_STA);
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return ret;
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}
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#if defined(CONFIG_I2C_MULTI_BUS)
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int i2c_set_bus_num(unsigned int bus)
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{
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if (bus > 1)
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return -1;
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i2c_bus_num = bus;
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i2c_init(i2c_bus_speed[bus], CONFIG_SYS_I2C_SLAVE);
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return 0;
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}
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int i2c_set_bus_speed(unsigned int speed)
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{
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i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
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return 0;
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}
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unsigned int i2c_get_bus_num(void)
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{
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return i2c_bus_num;
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}
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unsigned int i2c_get_bus_speed(void)
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{
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return i2c_bus_speed[i2c_bus_num];
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}
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#endif
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#endif /* CONFIG_HARD_I2C */
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