upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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429 lines
9.3 KiB
429 lines
9.3 KiB
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <fsl_ddr_sdram.h>
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#include <jffs2/load_kernel.h>
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#include <mtd_node.h>
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#include <flash.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#include <asm/fsl_pci.h>
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#endif
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#include "../common/qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
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setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
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return 0;
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}
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void board_config_serdes_mux(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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switch (srds_cfg) {
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/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 22:
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case 23:
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case 24:
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case 25:
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case 26:
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QIXIS_WRITE_I2C(brdcfg[4], 0x03);
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break;
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/* PEX(1) PEX(2) SGMII1 CPRI 1 */
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case 6:
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case 7:
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case 8:
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case 9:
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case 10:
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case 27:
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case 28:
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case 29:
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case 30:
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case 31:
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QIXIS_WRITE_I2C(brdcfg[4], 0x01);
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break;
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/* PEX(1) PEX(2) SGMII1 SGMII2 */
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case 11:
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case 32:
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QIXIS_WRITE_I2C(brdcfg[4], 0x00);
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break;
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/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
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case 12:
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case 13:
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case 14:
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case 15:
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case 16:
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case 33:
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case 34:
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case 35:
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case 36:
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case 37:
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QIXIS_WRITE_I2C(brdcfg[4], 0x07);
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break;
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/* PEX(1) SGMII2 SGMII1 CPRI 1 */
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case 17:
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case 18:
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case 19:
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case 20:
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case 21:
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case 38:
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case 39:
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case 40:
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case 41:
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case 42:
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QIXIS_WRITE_I2C(brdcfg[4], 0x05);
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break;
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/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
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case 43:
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case 44:
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case 45:
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case 46:
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case 47:
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QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
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break;
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default:
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break;
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}
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}
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/* Configure DSP DDR controller */
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void dsp_ddr_configure(void)
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{
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/*
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*There are separate DDR-controllers for DSP and PowerPC side DDR.
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*copy the ddr controller settings from PowerPC side DDR controller
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*to the DSP DDR controller as connected DDR memories are similar.
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*/
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struct ccsr_ddr __iomem *pa_ddr =
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(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
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struct ccsr_ddr temp_ddr;
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struct ccsr_ddr __iomem *dsp_ddr =
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(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
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memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
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temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
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temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
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memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
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dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
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}
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int board_early_init_r(void)
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{
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#ifndef CONFIG_SYS_NO_FLASH
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_64M, 1);
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set_tlb(1, flashbase + 0x4000000,
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CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
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#endif
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board_config_serdes_mux();
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dsp_ddr_configure();
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return 0;
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif /* ifdef CONFIG_PCI */
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int checkboard(void)
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{
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struct cpu_type *cpu;
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u8 sw;
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cpu = gd->arch.cpu;
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printf("Board: %sQDS\n", cpu->name);
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
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QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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printf("IFC chip select:");
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switch (sw) {
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case 0:
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printf("NOR\n");
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break;
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case 2:
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printf("Promjet\n");
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break;
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case 4:
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printf("NAND\n");
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break;
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default:
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printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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break;
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}
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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#endif
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#ifdef CONFIG_PCI
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pci_eth_init(bis);
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#endif
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return 0;
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}
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#define USBMUX_SEL_MASK 0xc0
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#define USBMUX_SEL_UART2 0xc0
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#define USBMUX_SEL_USB 0x40
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#define SPIMUX_SEL_UART3 0x80
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#define GPS_MUX_SEL_GPS 0x40
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#define TSEC_1588_CLKIN_MASK 0x03
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#define CON_XCVR_REF_CLK 0x00
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int misc_init_r(void)
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{
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u8 val;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 porbmsr = in_be32(&gur->porbmsr);
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u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
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/*Configure 1588 clock-in source from RF Card*/
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val = QIXIS_READ_I2C(brdcfg[5]);
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QIXIS_WRITE_I2C(brdcfg[5],
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(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
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if (hwconfig("uart2") && hwconfig("usb1")) {
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printf("UART2 and USB cannot work together on the board\n");
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printf("Remove one from hwconfig and reset\n");
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} else {
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if (hwconfig("uart2")) {
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val = QIXIS_READ_I2C(brdcfg[5]);
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QIXIS_WRITE_I2C(brdcfg[5],
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(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
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clrbits_be32(&gur->pmuxcr3,
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MPC85xx_PMUXCR3_USB_SEL_MASK);
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setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
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} else {
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/* By default USB should be selected.
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* Programming FPGA to select USB. */
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val = QIXIS_READ_I2C(brdcfg[5]);
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QIXIS_WRITE_I2C(brdcfg[5],
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(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
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}
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}
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if (hwconfig("sim")) {
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if (romloc == PORBMSR_ROMLOC_NAND_2K ||
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romloc == PORBMSR_ROMLOC_NOR ||
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romloc == PORBMSR_ROMLOC_SPI) {
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val = QIXIS_READ_I2C(brdcfg[3]);
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QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
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clrbits_be32(&gur->pmuxcr,
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MPC85xx_PMUXCR0_SIM_SEL_MASK);
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
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}
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}
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if (hwconfig("uart3")) {
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if (romloc == PORBMSR_ROMLOC_NAND_2K ||
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romloc == PORBMSR_ROMLOC_NOR ||
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romloc == PORBMSR_ROMLOC_SDHC) {
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/* UART3 and SPI1 (Flashes) are muxed together */
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val = QIXIS_READ_I2C(brdcfg[3]);
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QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
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clrbits_be32(&gur->pmuxcr3,
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MPC85xx_PMUXCR3_UART3_SEL_MASK);
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setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
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/* MUX to select UART3 connection to J24 header
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* or to GPS */
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val = QIXIS_READ_I2C(brdcfg[6]);
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if (hwconfig("gps"))
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QIXIS_WRITE_I2C(brdcfg[6],
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(val | GPS_MUX_SEL_GPS));
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else
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QIXIS_WRITE_I2C(brdcfg[6],
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(val & ~(GPS_MUX_SEL_GPS)));
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}
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}
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return 0;
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}
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void fdt_del_node_compat(void *blob, const char *compatible)
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{
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int err;
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int off = fdt_node_offset_by_compatible(blob, -1, compatible);
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if (off < 0) {
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printf("WARNING: could not find compatible node %s: %s.\n",
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compatible, fdt_strerror(off));
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return;
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}
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err = fdt_del_node(blob, off);
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if (err < 0) {
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printf("WARNING: could not remove %s: %s.\n",
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compatible, fdt_strerror(err));
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}
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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#ifdef CONFIG_FDT_FIXUP_PARTITIONS
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struct node_info nodes[] = {
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{ "cfi-flash", MTD_DEV_TYPE_NOR, },
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{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
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};
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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#if defined(CONFIG_PCI)
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FT_FSL_PCI_SETUP;
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#endif
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_FDT_FIXUP_PARTITIONS
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fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
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#endif
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 porbmsr = in_be32(&gur->porbmsr);
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u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
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if (!(hwconfig("uart2") && hwconfig("usb1"))) {
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/* If uart2 is there in hwconfig remove usb node from
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* device tree */
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if (hwconfig("uart2")) {
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/* remove dts usb node */
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fdt_del_node_compat(blob, "fsl-usb2-dr");
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} else {
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fsl_fdt_fixup_dr_usb(blob, bd);
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fdt_del_node_and_alias(blob, "serial2");
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}
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}
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if (hwconfig("uart3")) {
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if (romloc == PORBMSR_ROMLOC_NAND_2K ||
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romloc == PORBMSR_ROMLOC_NOR ||
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romloc == PORBMSR_ROMLOC_SDHC)
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/* Delete SPI node from the device tree */
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fdt_del_node_and_alias(blob, "spi1");
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} else
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fdt_del_node_and_alias(blob, "serial3");
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if (hwconfig("sim")) {
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if (romloc == PORBMSR_ROMLOC_NAND_2K ||
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romloc == PORBMSR_ROMLOC_NOR ||
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romloc == PORBMSR_ROMLOC_SPI) {
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/* remove dts sdhc node */
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fdt_del_node_compat(blob, "fsl,esdhc");
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} else if (romloc == PORBMSR_ROMLOC_SDHC) {
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/* remove dts sim node */
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fdt_del_node_compat(blob, "fsl,sim-v1.0");
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printf("SIM & SDHC can't work together on the board");
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printf("\nRemove sim from hwconfig and reset\n");
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}
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}
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return 0;
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}
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#endif
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