upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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53 lines
1.4 KiB
53 lines
1.4 KiB
/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/
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#ifdef CONFIG_SYS_FSL_DDR4
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{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
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{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
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{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
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{1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
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{1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
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#elif defined(CONFIG_SYS_FSL_DDR3)
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{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
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{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
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{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
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{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
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{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
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{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
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#else
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#error DDR type not defined
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#endif
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#endif
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