upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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506 lines
17 KiB
506 lines
17 KiB
/*
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* (C) Copyright 2000, 2001, 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
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* U-Boot port on RPXlite board
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define RPXClassic_50MHz
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1
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#define CONFIG_RPXCLASSIC 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
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/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
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#define CONFIG_FEC_ENET
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#ifdef CONFIG_FEC_ENET
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#define CFG_DISCOVER_PHY 1
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#define CONFIG_MII 1
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#endif /* CONFIG_FEC_ENET */
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/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */
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#if 1
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#define CONFIG_VIDEO_SED13806
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#define CONFIG_NEC_NL6448BC20
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#define CONFIG_VIDEO_SED13806_16BPP
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_SW_CURSOR
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#endif
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK 1
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"tftpboot; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_RESET_ADDRESS 0x80000000
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFA200000
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/*-----------------------------------------------------------------------------
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* I2C Configuration
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*-----------------------------------------------------------------------------
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*/
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#define CONFIG_I2C 1
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#define CFG_I2C_SPEED 50000
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#define CFG_I2C_SLAVE 0x34
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/* enable I2C and select the hardware/software driver */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00000010)
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#define I2C_TRISTATE (iop->pdir &= ~0x00000010)
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#define I2C_READ ((iop->pdat & 0x00000010) != 0)
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#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
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else iop->pdat &= ~0x00000010
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#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
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else iop->pdat &= ~0x00000020
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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# define CFG_I2C_SPEED 50000
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# define CFG_I2C_SLAVE 0x34
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# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
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# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFF000000
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#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE 0xFF000000
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/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#if 0
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x8000
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#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
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#else
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#define CFG_ENV_IS_IN_NVRAM 1
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#define CFG_ENV_ADDR 0xfa000100
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#define CFG_ENV_SIZE 0x1000
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWP)
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_MLRC10)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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*/
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/* up to 50 MHz we use a 1:1 clock */
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#define CFG_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF00
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/* up to 50 MHz we use a 1:1 clock */
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#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET 0x0100
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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/* #define CFG_DER 0x2002000F */
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#define CFG_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0 and OR0 (FLASH)
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*/
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#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
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#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
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/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
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#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
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/*
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* BR1 and OR1 (SDRAM)
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*
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*/
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#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
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#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CFG_OR_TIMING_SDRAM 0x00000E00
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#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
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#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
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/* RPXLITE mem setting */
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#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
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#define CFG_OR3_PRELIM 0xff7f8970
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#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
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#define CFG_OR4_PRELIM 0xFFF80970
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/* ECCX CS settings */
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#define SED13806_OR 0xFFC00108 /* - 4 Mo
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- Burst inhibit
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- external TA */
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#define SED13806_REG_ADDR 0xa0000000
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#define SED13806_ACCES 0x801 /* 16 bit access */
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/* Global definitions for the ECCX board */
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#define ECCX_CSR_ADDR (0xfac00000)
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#define ECCX_CSR8_OFFSET (0x8)
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#define ECCX_CSR11_OFFSET (0xB)
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#define ECCX_CSR12_OFFSET (0xC)
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#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
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#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
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#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
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#define REG_GPIO_CTRL 0x008
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/* Definitions for CSR8 */
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#define ECCX_ENEPSON 0x80 /* Bit 0:
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0= disable and reset SED1386
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1= enable SED1386 */
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/* Bit 1: 0= SED1386 in Big Endian mode */
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/* 1= SED1386 in little endian mode */
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#define ECCX_LE 0x40
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#define ECCX_BE 0x00
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/* Bit 2,3: Selection */
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/* 00 = Disabled */
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/* 01 = CS2 is used for the SED1386 */
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/* 10 = CS5 is used for the SED1386 */
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/* 11 = reserved */
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#define ECCX_CS2 0x10
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#define ECCX_CS5 0x20
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/* Definitions for CSR12 */
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#define ECCX_ID 0x02
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#define ECCX_860 0x01
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#define CFG_MAMR_PTA 58
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/*
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* Refresh clock Prescalar
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*/
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#define CFG_MPTPR MPTPR_PTP_DIV8
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/*
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* MAMR settings for SDRAM
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*/
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/* 10 column SDRAM */
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#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
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MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
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/* Configuration variable added by yooth. */
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/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
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/*
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* BCSRx
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*
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* Board Status and Control Registers
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*
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*/
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#define BCSR0 0xFA400000
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#define BCSR1 0xFA400001
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#define BCSR2 0xFA400002
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#define BCSR3 0xFA400003
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#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
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#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
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#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
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#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
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#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
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#define BCSR0_COLTEST 0x20
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#define BCSR0_ETHLPBK 0x40
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#define BCSR0_ETHEN 0x80
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#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
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#define BCSR1_PCVCTL6 0x02
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#define BCSR1_PCVCTL5 0x04
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#define BCSR1_PCVCTL4 0x08
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#define BCSR1_IPB5SEL 0x10
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#define BCSR2_MIIRST 0x80
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#define BCSR2_MIIPWRDWN 0x40
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#define BCSR2_MIICTL 0x08
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#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
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#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
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#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
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#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
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#define BCSR3_D27 0x10 /* Dip Switch settings */
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#define BCSR3_D26 0x20
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#define BCSR3_D25 0x40
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#define BCSR3_D24 0x80
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/*
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* Environment setting
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*/
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/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */
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/* #define CONFIG_IPADDR 10.10.106.1 */
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/* #define CONFIG_SERVERIP 10.10.104.11 */
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#endif /* __CONFIG_H */
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