upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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809 lines
22 KiB
809 lines
22 KiB
/**************************************************************************
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Etherboot - BOOTP/TFTP Bootstrap Program
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Skeleton NIC driver for Etherboot
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***************************************************************************/
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2, or (at
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* your option) any later version.
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*/
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/*
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* This file is a modified version from the Galileo polled mode
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* network driver for the ethernet contained within the GT64260
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* chip. It has been modified to fit into the U-Boot framework, from
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* the original (etherboot) setup. Also, additional cleanup and features
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* were added.
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*
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* - Josh Huber <huber@mclx.com>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <galileo/gt64260R.h>
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#include <galileo/core.h>
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#include <asm/cache.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include "eth.h"
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#include "eth_addrtbl.h"
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#if defined(CONFIG_CMD_NET)
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#define GT6426x_ETH_BUF_SIZE 1536
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/* if you like verbose output, turn this on! */
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#undef DEBUG
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/* Restart autoneg if we detect link is up on phy init. */
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/*
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* The GT doc's say that after Rst is deasserted, and the PHY
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* reports autoneg complete, it runs through its autoneg
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* procedures. This doesn't seem to be the case for MII
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* PHY's. To work around this check for link up && autoneg
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* complete when initilizing the port. If they are both set,
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* then restart PHY autoneg. Of course, it may be something
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* completly different.
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*/
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#ifdef CONFIG_ETHER_PORT_MII
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# define RESTART_AUTONEG
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#endif
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/* do this if you dont want to use snooping */
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#define USE_SOFTWARE_CACHE_MANAGEMENT
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#ifdef USE_SOFTWARE_CACHE_MANAGEMENT
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#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
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#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
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#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
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#else
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/* bummer - w/o flush, nothing works, even with snooping - FIXME */
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/* #define FLUSH_DCACHE(a,b) */
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#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
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#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
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#define INVALIDATE_DCACHE(a,b)
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#endif
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struct eth_dev_s {
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eth0_tx_desc_single *eth_tx_desc;
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eth0_rx_desc_single *eth_rx_desc;
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char *eth_tx_buffer;
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char *eth_rx_buffer[NR];
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int tdn, rdn;
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int dev;
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unsigned int reg_base;
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};
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#ifdef CONFIG_INTEL_LXT97X
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/* for intel LXT972 */
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static const char ether_port_phy_addr[3]={0,1,2};
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#else
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static const char ether_port_phy_addr[3]={4,5,6};
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#endif
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/* MII PHY access routines are common for all i/f, use gal_ent0 */
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#define GT6426x_MII_DEVNAME "gal_enet0"
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int gt6426x_miiphy_read(const char *devname, unsigned char phy,
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unsigned char reg, unsigned short *val);
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static inline unsigned short
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miiphy_read_ret(unsigned short phy, unsigned short reg)
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{
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unsigned short val;
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gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
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return val;
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}
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/**************************************************************************
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RESET - Reset adapter
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***************************************************************************/
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void
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gt6426x_eth_reset(void *v)
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{
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/* we should do something here...
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struct eth_device *wp = (struct eth_device *)v;
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struct eth_dev_s *p = wp->priv;
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*/
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printf ("RESET\n");
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/* put the card in its initial state */
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}
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static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
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{
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#ifdef DEBUG
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printf("SMI interrupt: ");
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if(icr&0x20000000) {
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printf("SMI done\n");
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}
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#endif
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if(icr&0x10000000) {
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#ifdef DEBUG
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unsigned int psr;
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psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
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printf("PHY state change:\n"
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" GT:%s:%s:%s:%s\n",
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psr & 1 ? "100" : " 10",
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psr & 8 ? " Link" : "nLink",
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psr & 2 ? "FD" : "HD",
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psr & 4 ? " FC" : "nFC");
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#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
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{
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unsigned short mii_11;
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mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11);
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printf(" mii:%s:%s:%s:%s %s:%s %s\n",
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mii_11 & (1 << 14) ? "100" : " 10",
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mii_11 & (1 << 10) ? " Link" : "nLink",
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mii_11 & (1 << 9) ? "FD" : "HD",
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mii_11 & (1 << 4) ? " FC" : "nFC",
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mii_11 & (1 << 7) ? "ANc" : "ANnc",
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mii_11 & (1 << 8) ? "AN" : "Manual",
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""
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);
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}
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#endif /* CONFIG_INTEL_LXT97X */
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#endif /* DEBUG */
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}
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}
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static int
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gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
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{
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int eth_len=0;
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char *eth_data;
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eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
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INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
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if (rx->command_status & 0x80000000) {
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return 0; /* No packet received */
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}
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eth_len = (unsigned int)
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(rx->buff_size_byte_count) & 0x0000ffff;
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eth_data = (char *) p->eth_rx_buffer[p->rdn];
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#ifdef DEBUG
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if (eth_len) {
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printf ("%s: Recived %d byte Packet @ 0x%p\n",
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__FUNCTION__, eth_len, eth_data);
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}
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#endif
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/*
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* packet is now in:
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* eth0_rx_buffer[RDN_ETH0];
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*/
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/* let the upper layer handle the packet */
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NetReceive ((uchar *)eth_data, eth_len);
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rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
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/* GT96100 Owner */
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rx->command_status = 0x80000000;
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FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
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p->rdn ++;
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if (p->rdn == NR) {p->rdn = 0;}
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sync();
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/* Start Rx*/
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GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
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#ifdef DEBUG
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{
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int i;
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for (i=0;i<12;i++) {
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printf(" %02x", eth_data[i]);
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}
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}
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printf(": %d bytes\n", eth_len);
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#endif
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INVALIDATE_DCACHE((unsigned int)eth_data,
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(unsigned int)eth_data+eth_len);
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return eth_len;
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}
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/**************************************************************************
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POLL - look for an rx frame, handle other conditions
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***************************************************************************/
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int
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gt6426x_eth_poll(void *v)
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{
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struct eth_device *wp = (struct eth_device *)v;
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struct eth_dev_s *p = wp->priv;
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unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
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if(icr) {
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GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
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#ifdef DEBUG
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printf("poll got ICR %08x\n", icr);
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#endif
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/* SMI done or PHY state change*/
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if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
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}
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/* always process. We aren't using RX interrupts */
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return gt6426x_eth_receive(p, icr);
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}
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/**************************************************************************
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TRANSMIT - Transmit a frame
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***************************************************************************/
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int
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gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
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{
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struct eth_device *wp = (struct eth_device *)v;
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struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
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#ifdef DEBUG
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unsigned int old_command_stat,old_psr;
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#endif
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eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
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/* wait for tx to be ready */
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INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
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while (tx->command_status & 0x80000000) {
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int i;
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for(i=0;i<1000;i++);
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INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
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}
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GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
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(unsigned int)tx);
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#ifdef DEBUG
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printf("copying to tx_buffer [%p], length %x, desc = %p\n",
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dev->eth_tx_buffer, s, dev->eth_tx_desc);
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#endif
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memcpy(dev->eth_tx_buffer, (char *) p, s);
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tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
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tx->bytecount_reserved = ((__u16)s) << 16;
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/* 31 - own
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* 22 - gencrc
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* 18:16 - pad, last, first */
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tx->command_status = (1<<31) | (1<<22) | (7<<16);
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#if 0
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/* FEr #18 */
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tx->next_desc = NULL;
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#else
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tx->next_desc =
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(struct eth0_tx_desc_struct *)
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&dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
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/* cpu owned */
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dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */
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#endif
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#ifdef DEBUG
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old_command_stat=tx->command_status,
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old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
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#endif
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FLUSH_DCACHE((unsigned int)tx,
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(unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
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FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
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GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
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#ifdef DEBUG
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{
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unsigned int command_stat=0;
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printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
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/* wait for tx to be ready */
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do {
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unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
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command_stat=tx->command_status;
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if(command_stat!=old_command_stat || psr !=old_psr) {
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printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
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old_command_stat = command_stat;
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old_psr = psr;
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}
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/* gt6426x_eth0_poll(); */
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} while (command_stat & 0x80000000);
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printf("sent %d byte frame\n", s);
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if((command_stat & (3<<15)) == 3) {
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printf("frame had error (stat=%08x)\n", command_stat);
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}
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}
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#endif
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return 0;
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}
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/**************************************************************************
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DISABLE - Turn off ethernet interface
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***************************************************************************/
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void
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gt6426x_eth_disable(void *v)
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{
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struct eth_device *wp = (struct eth_device *)v;
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struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
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GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
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}
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/**************************************************************************
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MII utilities - write: write to an MII register via SMI
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***************************************************************************/
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int
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gt6426x_miiphy_write(const char *devname, unsigned char phy,
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unsigned char reg, unsigned short data)
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{
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unsigned int temp= (reg<<21) | (phy<<16) | data;
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while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */
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GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
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return 0;
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}
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/**************************************************************************
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MII utilities - read: read from an MII register via SMI
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***************************************************************************/
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int
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gt6426x_miiphy_read(const char *devname, unsigned char phy,
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unsigned char reg, unsigned short *val)
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{
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unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
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while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */
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GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
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while(1) {
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temp=GTREGREAD(ETHERNET_SMI_REGISTER);
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if(temp & (1<<27)) break; /* wait for ReadValid */
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}
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*val = temp & 0xffff;
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return 0;
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}
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#ifdef DEBUG
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/**************************************************************************
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MII utilities - dump mii registers
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***************************************************************************/
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static void
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gt6426x_dump_mii(bd_t *bis, unsigned short phy)
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{
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printf("mii reg 0 - 3: %04x %04x %04x %04x\n",
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miiphy_read_ret(phy, 0x0),
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miiphy_read_ret(phy, 0x1),
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miiphy_read_ret(phy, 0x2),
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miiphy_read_ret(phy, 0x3)
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);
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printf(" 4 - 7: %04x %04x %04x %04x\n",
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miiphy_read_ret(phy, 0x4),
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miiphy_read_ret(phy, 0x5),
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miiphy_read_ret(phy, 0x6),
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miiphy_read_ret(phy, 0x7)
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);
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printf(" 8: %04x\n",
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miiphy_read_ret(phy, 0x8)
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);
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printf(" 16-19: %04x %04x %04x %04x\n",
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miiphy_read_ret(phy, 0x10),
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miiphy_read_ret(phy, 0x11),
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miiphy_read_ret(phy, 0x12),
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miiphy_read_ret(phy, 0x13)
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);
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printf(" 20,30: %04x %04x\n",
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miiphy_read_ret(phy, 20),
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miiphy_read_ret(phy, 30)
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);
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}
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#endif
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#ifdef RESTART_AUTONEG
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/* If link is up && autoneg compleate, and if
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* GT and PHY disagree about link capabilitys,
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* restart autoneg - something screwy with FD/HD
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* unless we do this. */
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static void
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check_phy_state(struct eth_dev_s *p)
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{
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int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR);
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int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
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if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) {
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int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) &
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miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA);
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int want;
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if (nego & LPA_100FULL) {
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want = 0x3;
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printf("MII: 100Base-TX, Full Duplex\n");
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} else if (nego & LPA_100HALF) {
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want = 0x1;
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printf("MII: 100Base-TX, Half Duplex\n");
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} else if (nego & LPA_10FULL) {
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want = 0x2;
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printf("MII: 10Base-T, Full Duplex\n");
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} else if (nego & LPA_10HALF) {
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want = 0x0;
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printf("MII: 10Base-T, Half Duplex\n");
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} else {
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printf("MII: Unknown link-foo! %x\n", nego);
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return;
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}
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if ((psr & 0x3) != want) {
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printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
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psr & 0x3, want);
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miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
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miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
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udelay(10000); /* the EVB's GT takes a while to notice phy
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went down and up */
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}
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}
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}
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#endif
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/**************************************************************************
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PROBE - Look for an adapter, this routine's visible to the outside
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***************************************************************************/
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int
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gt6426x_eth_probe(void *v, bd_t *bis)
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{
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struct eth_device *wp = (struct eth_device *)v;
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struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
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int dev = p->dev;
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unsigned int reg_base = p->reg_base;
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unsigned long temp;
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int i;
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if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
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{ /* This should never happen */
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printf("%s: Invalid device %d\n", __FUNCTION__, dev );
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return 0;
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}
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#ifdef DEBUG
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printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
|
|
printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
|
|
GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
|
|
GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
|
|
#endif
|
|
|
|
/* clear MIB counters */
|
|
for(i=0;i<255; i++)
|
|
temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
|
|
|
|
#ifdef CONFIG_INTEL_LXT97X
|
|
/* for intel LXT972 */
|
|
|
|
/* led 1: 0x1=txact
|
|
led 2: 0xc=link/rxact
|
|
led 3: 0x2=rxact (N/C)
|
|
strch: 0,2=30 ms, enable */
|
|
miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
|
|
|
|
/* 2.7ns port rise time */
|
|
/*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
|
|
#else
|
|
/* already set up in mpsc.c */
|
|
/*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */
|
|
|
|
/* already set up in sdram_init.S... */
|
|
/* MPSC0, MPSC1, RMII */
|
|
/*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */
|
|
#endif
|
|
GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
|
|
ether_port_phy_addr[0] |
|
|
(ether_port_phy_addr[1]<<5) |
|
|
(ether_port_phy_addr[2]<<10)); /* 2000 */
|
|
|
|
/* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes)
|
|
* 9 - 1: RIFB - interrupt on frame boundaries only
|
|
* 6:7 - 00: big endian rx and tx
|
|
* 5:2 - 1111: 15 retries */
|
|
GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
|
|
(2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */
|
|
|
|
#ifndef USE_SOFTWARE_CACHE_MANAGEMENT
|
|
/* enable rx/tx desc/buffer cache snoop */
|
|
GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
|
|
&temp); /* f200 */
|
|
temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
|
|
GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
|
|
temp);
|
|
#endif
|
|
|
|
/* 31 28 27 24 23 20 19 16
|
|
* 0000 0000 0000 0000 [0004]
|
|
* 15 12 11 8 7 4 3 0
|
|
* 1000 1101 0000 0000 [4d00]
|
|
* 20 - 0=MII 1=RMII
|
|
* 19 - 0=speed autoneg
|
|
* 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
|
|
* 11 - no force link pass
|
|
* 10 - 1=disable fctl autoneg
|
|
* 8 - override prio ?? */
|
|
temp = 0x00004d00;
|
|
#ifndef CONFIG_ETHER_PORT_MII
|
|
temp |= (1<<20); /* RMII */
|
|
#endif
|
|
/* set En */
|
|
GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
|
|
temp); /* 2408 */
|
|
|
|
/* hardcode E1 also? */
|
|
/* -- according to dox, this is safer due to extra pulldowns? */
|
|
if (dev<2) {
|
|
GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
|
|
temp); /* 2408 */
|
|
}
|
|
|
|
/* wake up MAC */ /* 2400 */
|
|
GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
|
|
temp |= (1<<7); /* enable port */
|
|
#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
|
|
temp |= (1<<12); /* hash size 1/2k */
|
|
#else
|
|
temp |= 1; /* promisc */
|
|
#endif
|
|
GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
|
|
/* 2400 */
|
|
|
|
#ifdef RESTART_AUTONEG
|
|
check_phy_state(p);
|
|
#endif
|
|
|
|
printf("%s: Waiting for link up..\n", wp->name);
|
|
temp = 10 * 1000;
|
|
/* wait for link back up */
|
|
while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
|
|
&& (--temp > 0)){
|
|
udelay(1000); /* wait 1 ms */
|
|
}
|
|
if ( temp == 0) {
|
|
printf("%s: Failed!\n", wp->name);
|
|
return (0);
|
|
}
|
|
|
|
printf("%s: OK!\n", wp->name);
|
|
|
|
p->tdn = 0;
|
|
p->rdn = 0;
|
|
p->eth_tx_desc[p->tdn].command_status = 0;
|
|
|
|
/* Initialize Rx Side */
|
|
for (temp = 0; temp < NR; temp++) {
|
|
p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
|
|
p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
|
|
|
|
/* GT96100 Owner */
|
|
p->eth_rx_desc[temp].command_status = 0x80000000;
|
|
p->eth_rx_desc[temp].next_desc =
|
|
(struct eth0_rx_desc_struct *)
|
|
&p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
|
|
}
|
|
|
|
FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
|
|
(unsigned int)&p->eth_tx_desc[NR]);
|
|
FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
|
|
(unsigned int)&p->eth_rx_desc[NR]);
|
|
|
|
GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
|
|
(unsigned int) p->eth_tx_desc);
|
|
GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
|
|
(unsigned int) p->eth_rx_desc);
|
|
GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
|
|
(unsigned int) p->eth_rx_desc);
|
|
|
|
#ifdef DEBUG
|
|
printf ("\nRx descriptor pointer is %08x %08x\n",
|
|
GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
|
|
GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
|
|
printf ("\n\n%08x %08x\n",
|
|
(unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
|
|
|
|
printf ("Descriptor dump:\n");
|
|
printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
|
|
printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
|
|
printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
|
|
printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
|
|
printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
|
|
printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
|
|
printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
|
|
printf ("%08x\n\n",
|
|
*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
|
|
#endif
|
|
|
|
#ifdef DEBUG
|
|
gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
|
|
#endif
|
|
|
|
#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
|
|
{
|
|
unsigned int hashtable_base;
|
|
u8 *b = (u8 *)(wp->enetaddr);
|
|
u32 macH, macL;
|
|
|
|
/* twist the MAC up into the way the discovery wants it */
|
|
macH= (b[0]<<8) | b[1];
|
|
macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
|
|
|
|
/* mode 0, size 0x800 */
|
|
hashtable_base =initAddressTable(dev,0,1);
|
|
|
|
if(!hashtable_base) {
|
|
printf("initAddressTable failed\n");
|
|
return 0;
|
|
}
|
|
|
|
addAddressTableEntry(dev, macH, macL, 1, 0);
|
|
GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
|
|
hashtable_base);
|
|
}
|
|
#endif
|
|
|
|
/* Start Rx*/
|
|
GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
|
|
printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
|
|
return 1;
|
|
}
|
|
|
|
/* enter all the galileo ethernet devs into MULTI-BOOT */
|
|
void
|
|
gt6426x_eth_initialize(bd_t *bis)
|
|
{
|
|
struct eth_device *dev;
|
|
struct eth_dev_s *p;
|
|
int devnum, x, temp;
|
|
char *s, *e, buf[64];
|
|
|
|
#ifdef DEBUG
|
|
printf( "\n%s\n", __FUNCTION );
|
|
#endif
|
|
|
|
for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
|
|
dev = calloc(sizeof(*dev), 1);
|
|
if (!dev) {
|
|
printf( "%s: gal_enet%d allocation failure, %s\n",
|
|
__FUNCTION__, devnum, "eth_device structure");
|
|
return;
|
|
}
|
|
|
|
/* must be less than sizeof(dev->name) */
|
|
sprintf(dev->name, "gal_enet%d", devnum);
|
|
|
|
#ifdef DEBUG
|
|
printf( "Initializing %s\n", dev->name );
|
|
#endif
|
|
|
|
/* Extract the MAC address from the environment */
|
|
switch (devnum)
|
|
{
|
|
case 0: s = "ethaddr"; break;
|
|
#if (GAL_ETH_DEVS > 1)
|
|
case 1: s = "eth1addr"; break;
|
|
#endif
|
|
#if (GAL_ETH_DEVS > 2)
|
|
case 2: s = "eth2addr"; break;
|
|
#endif
|
|
default: /* this should never happen */
|
|
printf( "%s: Invalid device number %d\n",
|
|
__FUNCTION__, devnum );
|
|
return;
|
|
}
|
|
|
|
temp = getenv_f(s, buf, sizeof(buf));
|
|
s = (temp > 0) ? buf : NULL;
|
|
|
|
#ifdef DEBUG
|
|
printf ("Setting MAC %d to %s\n", devnum, s );
|
|
#endif
|
|
for (x = 0; x < 6; ++x) {
|
|
dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
|
|
if (s)
|
|
s = (*e) ? e+1 : e;
|
|
}
|
|
|
|
dev->init = (void*)gt6426x_eth_probe;
|
|
dev->halt = (void*)gt6426x_eth_reset;
|
|
dev->send = (void*)gt6426x_eth_transmit;
|
|
dev->recv = (void*)gt6426x_eth_poll;
|
|
|
|
p = calloc( sizeof(*p), 1 );
|
|
dev->priv = (void*)p;
|
|
if (!p)
|
|
{
|
|
printf( "%s: %s allocation failure, %s\n",
|
|
__FUNCTION__, dev->name, "Private Device Structure");
|
|
free(dev);
|
|
return;
|
|
}
|
|
|
|
p->dev = devnum;
|
|
p->tdn=0;
|
|
p->rdn=0;
|
|
p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
|
|
|
|
p->eth_tx_desc =
|
|
(eth0_tx_desc_single *)
|
|
(((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
|
|
(NT+1)) & 0xfffffff0) + 0x10);
|
|
if (!p)
|
|
{
|
|
printf( "%s: %s allocation failure, %s\n",
|
|
__FUNCTION__, dev->name, "Tx Descriptor");
|
|
free(dev);
|
|
return;
|
|
}
|
|
|
|
p->eth_rx_desc =
|
|
(eth0_rx_desc_single *)
|
|
(((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
|
|
(NR+1)) & 0xfffffff0) + 0x10);
|
|
if (!p->eth_rx_desc)
|
|
{
|
|
printf( "%s: %s allocation failure, %s\n",
|
|
__FUNCTION__, dev->name, "Rx Descriptor");
|
|
free(dev);
|
|
free(p);
|
|
return;
|
|
}
|
|
|
|
p->eth_tx_buffer =
|
|
(char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
|
|
if (!p->eth_tx_buffer)
|
|
{
|
|
printf( "%s: %s allocation failure, %s\n",
|
|
__FUNCTION__, dev->name, "Tx Bufffer");
|
|
free(dev);
|
|
free(p);
|
|
free(p->eth_rx_desc);
|
|
return;
|
|
}
|
|
|
|
for (temp = 0 ; temp < NR ; temp ++) {
|
|
p->eth_rx_buffer[temp] =
|
|
(char *)
|
|
(((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
|
|
if (!p->eth_rx_buffer[temp])
|
|
{
|
|
printf( "%s: %s allocation failure, %s\n",
|
|
__FUNCTION__, dev->name, "Rx Buffers");
|
|
free(dev);
|
|
free(p);
|
|
free(p->eth_tx_buffer);
|
|
free(p->eth_rx_desc);
|
|
free(p->eth_tx_desc);
|
|
while (temp >= 0)
|
|
free(p->eth_rx_buffer[--temp]);
|
|
return;
|
|
}
|
|
}
|
|
|
|
|
|
eth_register(dev);
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
miiphy_register(dev->name,
|
|
gt6426x_miiphy_read, gt6426x_miiphy_write);
|
|
#endif
|
|
}
|
|
|
|
}
|
|
#endif
|
|
|