upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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396 lines
11 KiB
396 lines
11 KiB
/*
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/ic/sc520.h>
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#include <ali512x.h>
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#include <spi.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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#undef SC520_CDP_DEBUG
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#ifdef SC520_CDP_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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/* ------------------------------------------------------------------------- */
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/*
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* Theory:
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* We first set up all IRQs to be non-pci, edge triggered,
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* when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
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* called we reallocate irqs to the pci bus with sc520_pci_set_irq()
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* as needed. Whe choose the irqs to gram from a configurable list
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* inside pci_sc520_fixup_irq() (If this list contains stupid irq's
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* such as 0 thngas will not work)
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*/
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static void irq_init(void)
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{
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/* disable global interrupt mode */
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sc520_mmcr->picicr = 0x40;
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/* set all irqs to edge */
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sc520_mmcr->pic_mode[0] = 0x00;
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sc520_mmcr->pic_mode[1] = 0x00;
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sc520_mmcr->pic_mode[2] = 0x00;
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/* active low polarity on PIC interrupt pins,
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* active high polarity on all other irq pins */
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sc520_mmcr->intpinpol = 0x0000;
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/* set irq number mapping */
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sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED; /* disable GP timer 0 INT */
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sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED; /* disable GP timer 1 INT */
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sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED; /* disable GP timer 2 INT */
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sc520_mmcr->pit_int_map[0] = SC520_IRQ0; /* Set PIT timer 0 INT to IRQ0 */
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sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED; /* disable PIT timer 1 INT */
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sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED; /* disable PIT timer 2 INT */
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sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED; /* disable PCI INT A */
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sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED; /* disable PCI INT B */
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sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED; /* disable PCI INT C */
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sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED; /* disable PCI INT D */
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sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED; /* disable DMA INT */
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sc520_mmcr->ssimap = SC520_IRQ_DISABLED; /* disable Synchronius serial INT */
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sc520_mmcr->wdtmap = SC520_IRQ_DISABLED; /* disable Watchdog INT */
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sc520_mmcr->rtcmap = SC520_IRQ8; /* Set RTC int to 8 */
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sc520_mmcr->wpvmap = SC520_IRQ_DISABLED; /* disable write protect INT */
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sc520_mmcr->icemap = SC520_IRQ1; /* Set ICE Debug Serielport INT to IRQ1 */
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sc520_mmcr->ferrmap = SC520_IRQ13; /* Set FP error INT to IRQ13 */
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if (CONFIG_SYS_USE_SIO_UART) {
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sc520_mmcr->uart_int_map[0] = SC520_IRQ_DISABLED; /* disable internal UART1 INT */
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sc520_mmcr->uart_int_map[1] = SC520_IRQ_DISABLED; /* disable internal UART2 INT */
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sc520_mmcr->gp_int_map[3] = SC520_IRQ3; /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
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sc520_mmcr->gp_int_map[4] = SC520_IRQ4; /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
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} else {
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sc520_mmcr->uart_int_map[0] = SC520_IRQ4; /* Set internal UART2 INT to IRQ4 */
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sc520_mmcr->uart_int_map[1] = SC520_IRQ3; /* Set internal UART2 INT to IRQ3 */
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sc520_mmcr->gp_int_map[3] = SC520_IRQ_DISABLED; /* disable GPIRQ3 (ISA IRQ3) */
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sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED; /* disable GPIRQ4 (ISA IRQ4) */
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}
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sc520_mmcr->gp_int_map[1] = SC520_IRQ1; /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
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sc520_mmcr->gp_int_map[5] = SC520_IRQ5; /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
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sc520_mmcr->gp_int_map[6] = SC520_IRQ6; /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
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sc520_mmcr->gp_int_map[7] = SC520_IRQ7; /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
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sc520_mmcr->gp_int_map[8] = SC520_IRQ8; /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
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sc520_mmcr->gp_int_map[9] = SC520_IRQ9; /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
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sc520_mmcr->gp_int_map[0] = SC520_IRQ11; /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
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sc520_mmcr->gp_int_map[2] = SC520_IRQ12; /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
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sc520_mmcr->gp_int_map[10] = SC520_IRQ14; /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
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sc520_mmcr->pcihostmap = 0x11f; /* Map PCI hostbridge INT to NMI */
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sc520_mmcr->eccmap = 0x100; /* Map SDRAM ECC failure INT to NMI */
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}
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static void silence_uart(int port)
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{
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outb(0, port+1);
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}
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void setup_ali_sio(int uart_primary)
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{
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ali512x_init();
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ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
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ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
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ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
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ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
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ali512x_set_rtc(ALI_DISABLED, 0, 0);
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ali512x_set_kbc(ALI_ENABLED, 1, 12);
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ali512x_set_cio(ALI_ENABLED);
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/* IrDa pins */
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ali512x_cio_function(12, 1, 0, 0);
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ali512x_cio_function(13, 1, 0, 0);
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/* SSI chip select pins */
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ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */
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ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */
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ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */
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/* Board REV pins */
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ali512x_cio_function(20, 0, 0, 1);
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ali512x_cio_function(21, 0, 0, 1);
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ali512x_cio_function(22, 0, 0, 1);
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ali512x_cio_function(23, 0, 0, 1);
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}
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/* set up the ISA bus timing and system address mappings */
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static void bus_init(void)
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{
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/* set up the GP IO pins */
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sc520_mmcr->piopfs31_16 = 0xf7ff; /* set the GPIO pin function 31-16 reg */
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sc520_mmcr->piopfs15_0 = 0xffff; /* set the GPIO pin function 15-0 reg */
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sc520_mmcr->cspfs = 0xf8; /* set the CS pin function reg */
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sc520_mmcr->clksel = 0x70;
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sc520_mmcr->gpcsrt = 1; /* set the GP CS offset */
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sc520_mmcr->gpcspw = 3; /* set the GP CS pulse width */
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sc520_mmcr->gpcsoff = 1; /* set the GP CS offset */
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sc520_mmcr->gprdw = 3; /* set the RD pulse width */
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sc520_mmcr->gprdoff = 1; /* set the GP RD offset */
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sc520_mmcr->gpwrw = 3; /* set the GP WR pulse width */
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sc520_mmcr->gpwroff = 1; /* set the GP WR offset */
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sc520_mmcr->bootcsctl = 0x1823; /* set up timing of BOOTCS */
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sc520_mmcr->romcs1ctl = 0x1823; /* set up timing of ROMCS1 */
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sc520_mmcr->romcs2ctl = 0x1823; /* set up timing of ROMCS2 */
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/* adjust the memory map:
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* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
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* and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
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* we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
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/* SRAM = GPCS3 128k @ d0000-effff*/
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sc520_mmcr->par[2] = 0x4e00400d;
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/* IDE0 = GPCS6 1f0-1f7 */
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sc520_mmcr->par[3] = 0x380801f0;
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/* IDE1 = GPCS7 3f6 */
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sc520_mmcr->par[4] = 0x3c0003f6;
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/* bootcs */
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sc520_mmcr->par[12] = 0x8bffe800;
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/* romcs2 */
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sc520_mmcr->par[13] = 0xcbfff000;
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/* romcs1 */
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sc520_mmcr->par[14] = 0xabfff800;
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/* 680 LEDS */
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sc520_mmcr->par[15] = 0x30000640;
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sc520_mmcr->adddecctl = 0;
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asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
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if (CONFIG_SYS_USE_SIO_UART) {
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sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | UART2_DIS | UART1_DIS;
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setup_ali_sio(1);
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} else {
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sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
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setup_ali_sio(0);
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silence_uart(0x3e8);
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silence_uart(0x2e8);
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}
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}
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/* GPCS usage
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* GPCS0 PIO27 (NMI)
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* GPCS1 ROMCS1
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* GPCS2 ROMCS2
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* GPCS3 SRAMCS PAR2
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* GPCS4 unused PAR3
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* GPCS5 unused PAR4
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* GPCS6 IDE
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* GPCS7 IDE
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*/
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/* par usage:
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* PAR0 legacy_video
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* PAR1 PCI ROM mapping
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* PAR2 SRAM
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* PAR3 IDE
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* PAR4 IDE
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* PAR5 legacy_video
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* PAR6 legacy_video
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* PAR7 legacy_video
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* PAR8 legacy_video
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* PAR9 legacy_video
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* PAR10 legacy_video
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* PAR11 ISAROM
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* PAR12 BOOTCS
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* PAR13 ROMCS1
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* PAR14 ROMCS2
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* PAR15 Port 0x680 LED display
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*/
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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init_sc520();
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bus_init();
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irq_init();
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/* max drive current on SDRAM */
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sc520_mmcr->dsctl = 0x0100;
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/* enter debug mode after next reset (only if jumper is also set) */
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sc520_mmcr->rescfg = 0x08;
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/* configure the software timer to 33.333MHz */
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sc520_mmcr->swtmrcfg = 0;
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gd->bus_clk = 33333000;
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return 0;
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}
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int dram_init(void)
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{
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init_sc520_dram();
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return 0;
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}
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void show_boot_progress(int val)
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{
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if (val < -32) val = -1; /* let things compatible */
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outb(val&0xff, 0x80);
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outb((val&0xff00)>>8, 0x680);
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}
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int last_stage_init(void)
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{
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int minor;
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int major;
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major = minor = 0;
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major |= ali512x_cio_in(23)?2:0;
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major |= ali512x_cio_in(22)?1:0;
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minor |= ali512x_cio_in(21)?2:0;
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minor |= ali512x_cio_in(20)?1:0;
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printf("AMD SC520 CDP revision %d.%d\n", major, minor);
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return 0;
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}
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void ssi_chip_select(int dev)
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{
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/* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
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switch (dev) {
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case 1: /* SPI EEPROM */
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ali512x_cio_out(16, 0);
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break;
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case 2: /* MW EEPROM */
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ali512x_cio_out(15, 1);
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break;
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case 3: /* AUX */
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ali512x_cio_out(14, 1);
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break;
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case 0:
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ali512x_cio_out(16, 1);
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ali512x_cio_out(15, 0);
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ali512x_cio_out(14, 0);
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break;
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default:
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printf("Illegal SSI device requested: %d\n", dev);
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}
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}
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void spi_eeprom_probe(int x)
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{
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}
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int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
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{
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return 0;
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}
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int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
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{
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return 0;
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}
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void spi_init_f(void)
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{
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#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
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spi_eeprom_probe(1);
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#endif
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#ifdef CONFIG_SYS_SC520_CDP_USE_MW
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mw_eeprom_probe(2);
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#endif
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}
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ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
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{
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int offset;
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int i;
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ssize_t res;
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offset = 0;
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for (i=0;i<alen;i++) {
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offset <<= 8;
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offset |= addr[i];
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}
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#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
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res = spi_eeprom_read(1, offset, buffer, len);
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#endif
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#ifdef CONFIG_SYS_SC520_CDP_USE_MW
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res = mw_eeprom_read(2, offset, buffer, len);
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#endif
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#if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
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res = 0;
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#endif
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return res;
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}
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ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
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{
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int offset;
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int i;
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ssize_t res;
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offset = 0;
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for (i=0;i<alen;i++) {
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offset <<= 8;
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offset |= addr[i];
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}
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#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
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res = spi_eeprom_write(1, offset, buffer, len);
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#endif
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#ifdef CONFIG_SYS_SC520_CDP_USE_MW
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res = mw_eeprom_write(2, offset, buffer, len);
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#endif
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#if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
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res = 0;
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#endif
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return res;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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