upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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116 lines
4.5 KiB
116 lines
4.5 KiB
/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP24XX_CLOCKS_H_
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#define _OMAP24XX_CLOCKS_H_
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#define COMMIT_DIVIDERS 0x1
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#define MODE_BYPASS_FAST 0x2
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#define APLL_LOCK 0xc
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#ifdef CONFIG_APTIX
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#define DPLL_LOCK 0x1 /* stay in bypass mode */
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#else
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#define DPLL_LOCK 0x3 /* DPLL lock */
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#endif
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/****************************************************************************;
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; PRCM Scheme II
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;
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; Enable clocks and DPLL for:
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; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
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; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
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; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
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; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
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; DSPI=100 6 CM_CLKSEL_DSP[6:5]
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; DSP_S bypass CM_CLKSEL_DSP[7]
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; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
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; IVAF=100 auto
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; IVAI auto
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; IVA_MPU auto
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; IVA_S bypass CM_CLKSEL_DSP[13]
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; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
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; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
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; SSI_SSTF=100 auto
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; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
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; L4=100Mhz 6
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; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
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***************************************************************************/
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#define II_DPLL_OUT_X2 0x2 /* x2 core out */
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#define II_MPU_DIV 0x2 /* mpu = core/2 */
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#define II_DSP_DIV 0x343 /* dsp & iva divider */
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#define II_GFX_DIV 0x2
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#define II_BUS_DIV 0x04600C26
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#define II_BUS_DIV_ES1 0x04601026
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#define II_DPLL_300 0x01832100
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/****************************************************************************;
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; PRCM Scheme III
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;
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; Enable clocks and DPLL for:
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; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
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; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
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; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
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; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
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; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
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; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
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; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
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; IVAF=88.67 auto
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; IVAI auto
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; IVA_MPU auto
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; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
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; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
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; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
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; SSI_SSTF=88.67 auto
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; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
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; L4=66.5Mhz /8
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; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
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***************************************************************************/
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#define III_DPLL_OUT_X2 0x2 /* x2 core out */
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#define III_MPU_DIV 0x2 /* mpu = core/2 */
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#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
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#define III_GFX_DIV 0x2
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#define III_BUS_DIV 0x08300c44
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#define III_BUS_DIV_ES1 0x08301044
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#define III_DPLL_266 0x01885500
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/* set defaults for boot up */
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#ifdef PRCM_CONFIG_II
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# define DPLL_OUT II_DPLL_OUT_X2
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# define MPU_DIV II_MPU_DIV
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# define DSP_DIV II_DSP_DIV
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# define GFX_DIV II_GFX_DIV
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# define BUS_DIV II_BUS_DIV
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# define BUS_DIV_ES1 II_BUS_DIV_ES1
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# define DPLL_VAL II_DPLL_300
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#elif PRCM_CONFIG_III
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# define DPLL_OUT III_DPLL_OUT_X2
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# define MPU_DIV III_MPU_DIV
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# define DSP_DIV III_DSP_DIV
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# define GFX_DIV III_GFX_DIV
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# define BUS_DIV III_BUS_DIV
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# define BUS_DIV_ES1 III_BUS_DIV_ES1
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# define DPLL_VAL III_DPLL_266
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#endif
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/* lock delay time out */
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#define LDELAY 12000000
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#endif
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