upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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297 lines
10 KiB
297 lines
10 KiB
/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1
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#define CONFIG_AMX860 1
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#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */
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#undef CONFIG_8xx_CONS_SMC2
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#define CONFIG_8xx_CONS_SCC2 1
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define MPC8XX_FACT 10 /* Multiply by 10 */
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#define MPC8XX_XIN 5000000 /* 5 MHz in */
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
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"bootm" /* autoboot command */
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#undef CONFIG_BOOTARGS
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
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#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_DHCP | \
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CFG_CMD_DATE | \
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CFG_CMD_NFS | \
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CFG_CMD_SNTP )
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#if defined(DEBUG)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* U-Boot for AMX board supports two types of memory extension
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* modules: one that provides 4 MB flash memory, and another one with
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* 16 MB EDO DRAM.
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*
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* The flash module swaps the CS0 and CS1 signals: if the module is
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* installed, CS0 is connected to Flash on the module and CS1 is
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* connected to the on-board Flash. This means that you must intall
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* U-Boot when the Flash module is plugged in, if you plan to use
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* it.
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*
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* To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
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* must be defined. The DRAM module uses CS1.
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*
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* Only one of these modules may be installed at a time. If U-Boot
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* is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
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* work if the Flash extension module is installed instead of the
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* DRAM module.
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*/
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#define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*
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* Use 4 MB for without and 8 MB with 16 MB DRAM extension module
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* (CONFIG_AMX_RAM_EXT)
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*/
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#ifdef CONFIG_AMX_RAM_EXT
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# define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#else
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# define CFG_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* set the PLL, the low-power modes and the reset control (15-29)
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*/
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#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
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#define CFG_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
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#ifndef CONFIG_AMX_RAM_EXT
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#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
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#endif
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
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/* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM 0xFFC00954 /* Real values for the board */
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#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
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#ifndef CONFIG_AMX_RAM_EXT
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#define CFG_OR1_REMAP CFG_OR0_REMAP
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#define CFG_OR1_PRELIM 0xFFC00954 /* Real values for the board */
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#define CFG_BR1_PRELIM 0x60000001 /* Real values for the board */
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#endif
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/* DSP ("Glue") Xilinx */
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#define CFG_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */
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#define CFG_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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