upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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525 lines
17 KiB
525 lines
17 KiB
/*
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* (C) Copyright 2005
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* Heiko Schocher, DENX Software Engineering, <hs@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
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#define CONFIG_MPC8272_FAMILY 1
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#define CONFIG_IDS8247 1
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#define CPU_ID_STR "MPC8247"
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTCOUNT_LIMIT
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath)\0" \
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"ramargs=setenv bootargs root=/dev/ram rw " \
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"console=ttyS0,115200\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
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":$(hostname):$(netdev):off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm $(kernel_addr)\0" \
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"flash_self=run ramargs addip;" \
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"bootm $(kernel_addr) $(ramdisk_addr)\0" \
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"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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"bootfile=/tftpboot/IDS8247/uImage\0" \
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"kernel_addr=ff800000\0" \
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"ramdisk_addr=ffa00000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_MISC_INIT_R 1
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00000080)
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#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
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#define I2C_READ ((iop->pdat & 0x00000080) != 0)
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#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
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else iop->pdat &= ~0x00000080
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#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
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else iop->pdat &= ~0x00000100
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#if 0
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#define CFG_I2C_EEPROM_ADDR 0x50
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CONFIG_I2C_X
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#endif
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/*
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* select serial console configuration
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* use the extern UART for the console
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/*
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* NS16550 Configuration
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*/
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK 14745600
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#define CFG_UART_BASE 0xE0000000
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#define CFG_UART_SIZE 0x10000
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#define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000)
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
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* from CONFIG_COMMANDS to remove support for networking.
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*
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
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#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
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* - Enable Full Duplex in FSMR
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*/
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# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
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# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
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# define CFG_CPMFCR_RAMTYPE 0
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# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
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/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
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#define CONFIG_8260_CLKIN 66666666 /* in Hz */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_DHCP | \
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CFG_CMD_NFS | \
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CFG_CMD_NAND | \
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CFG_CMD_I2C | \
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CFG_CMD_SNTP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/* What should the base address of the main FLASH be and how big is
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* it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
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* The main FLASH is whichever is connected to *CS0.
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*/
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#define CFG_FLASH0_BASE 0xFFF00000
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#define CFG_FLASH0_SIZE 8
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/* Flash bank size (for preliminary settings)
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*/
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#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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/* Environment in flash */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x60000)
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#define CFG_ENV_SIZE 0x20000
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#define CFG_ENV_SECT_SIZE 0x20000
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/*-----------------------------------------------------------------------
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* NAND-FLASH stuff
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*-----------------------------------------------------------------------
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#define CFG_NAND0_BASE 0xE1000000
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define NAND_NO_RB
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define NAND_DISABLE_CE(nand) do \
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{ \
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*(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
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} while(0)
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#define NAND_ENABLE_CE(nand) do \
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{ \
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*(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
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} while(0)
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#define NAND_CTL_CLRALE(nandptr) do \
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{ \
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*(((volatile __u8 *)nandptr) + 0x8) = 0; \
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} while(0)
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#define NAND_CTL_SETALE(nandptr) do \
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{ \
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*(((volatile __u8 *)nandptr) + 0x9) = 0; \
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} while(0)
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#define NAND_CTL_CLRCLE(nandptr) do \
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{ \
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*(((volatile __u8 *)nandptr) + 0x8) = 0; \
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} while(0)
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#define NAND_CTL_SETCLE(nandptr) do \
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{ \
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*(((volatile __u8 *)nandptr) + 0xa) = 0; \
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} while(0)
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#ifdef NAND_NO_RB
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/* constant delay (see also tR in the datasheet) */
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#define NAND_WAIT_READY(nand) do { \
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udelay(12); \
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} while (0)
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#else
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/* use the R/B pin */
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#endif
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#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
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#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
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#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
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#endif /* CFG_CMD_NAND */
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*
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* if you change bits in the HRCW, you must also change the CFG_*
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* defines for the various registers affected by the HRCW e.g. changing
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* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
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*/
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#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
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/* no slaves so just fill with zeros */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF0000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*
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* 60x SDRAM is mapped at CFG_SDRAM_BASE
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE CFG_FLASH0_BASE
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
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#define CFG_HID0_FINAL 0
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#define CFG_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CFG_RMR 0
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define CFG_BCR 0
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 4-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
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#else
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#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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* Ensure DFBRG is Divide by 16
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*/
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#define CFG_SCCR (0x00000028 | SCCR_DFBRG01)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CFG_RCCR 0
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 16 bit FLASH
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* 1 60x GPCM 8 bit NAND
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* 2 60x SDRAM 32 bit SDRAM
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* 3 60x GPCM 8 bit UART
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*
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*/
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#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
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/* Minimum mask to separate preliminary
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* address ranges for CS[0:2]
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*/
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#define CFG_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
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#define CFG_MPTPR 0x6600
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/*-----------------------------------------------------------------------------
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* Address for Mode Register Set (MRS) command
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*-----------------------------------------------------------------------------
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*/
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#define CFG_MRS_OFFS 0x00000110
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/* Bank 0 - FLASH
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*/
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
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ORxG_SCY_6_CLK )
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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/* Bank 1 - NAND Flash
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*/
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#define CFG_NAND_BASE CFG_NAND0_BASE
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#define CFG_NAND_SIZE 0x8000
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#define CFG_OR_TIMING_NAND 0x000036
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#define CFG_BR1_PRELIM ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
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#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
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#endif
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/* Bank 2 - 60x bus SDRAM
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*/
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#define CFG_PSRT 0x20
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#define CFG_LSRT 0x20
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#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_32 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CFG_OR2_PRELIM CFG_OR2
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/* SDRAM initialization values
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*/
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#define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI0_A10 |\
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ORxS_NUMR_12)
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#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\
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PSDMR_BSMA_A15_A17 |\
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PSDMR_SDA10_PBI0_A11 |\
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PSDMR_RFRC_5_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_BL |\
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PSDMR_LDOTOPRE_2C |\
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PSDMR_WRC_3C |\
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PSDMR_CL_3)
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/* Bank 3 - UART
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*/
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#define CFG_BR3_PRELIM ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
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#define CFG_OR3_PRELIM (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
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#endif /* __CONFIG_H */
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