upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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459 lines
16 KiB
459 lines
16 KiB
/*
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* U-Boot configuration for SIXNET SXNI855T CPU board.
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* This board is based (loosely) on the Motorola FADS board, so this
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* file is based (loosely) on config_FADS860T.h, see it for additional
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* credits.
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*
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* Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/*
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* Memory map:
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*
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* ff100000 -> ff13ffff : FPGA CS1
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* ff030000 -> ff03ffff : EXPANSION CS7
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* ff020000 -> ff02ffff : DATA FLASH CS4
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* ff018000 -> ff01ffff : UART B CS6/UPMB
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* ff010000 -> ff017fff : UART A CS5/UPMB
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* ff000000 -> ff00ffff : IMAP internal to the MPC855T
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* f8000000 -> fbffffff : FLASH CS0 up to 64MB
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* f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
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* 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#include <mpc8xx_irq.h>
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#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */
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/* The 855T is just a stripped 860T and needs code for 860, so for now
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* at least define 860, 860T and 855T
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*/
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#define CONFIG_MPC860 1
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#define CONFIG_MPC860T 1
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#define CONFIG_MPC855T 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_SCC1
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_HAS_ETH1
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/*-----------------------------------------------------------------------
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* Definitions for status LED
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*/
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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# define STATUS_LED_PAR im_ioport.iop_papar
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# define STATUS_LED_DIR im_ioport.iop_padir
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# define STATUS_LED_ODR im_ioport.iop_paodr
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# define STATUS_LED_DAT im_ioport.iop_padat
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# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */
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# define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
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# define STATUS_LED_STATE STATUS_LED_BLINKING
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# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
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# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
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#ifdef DEV /* development (debug) settings */
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#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF
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#else /* production settings */
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#define CONFIG_BOOT_LED_STATE STATUS_LED_ON
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#endif
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#define CONFIG_SHOW_BOOT_PROGRESS 1
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#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/ram ip=off"
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#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
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#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */
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#define CONFIG_SOFT_I2C /* I2C bit-banged */
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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# define CFG_I2C_SPEED 50000
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# define CFG_I2C_SLAVE 0xFE
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# define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */
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# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
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#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
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#define CFG_DISCOVER_PHY
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_EEPROM | \
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CFG_CMD_JFFS2 | \
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CFG_CMD_NAND | \
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CFG_CMD_DATE)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CFG_JFFS2_SORT_FRAGMENTS
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/*
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* JFFS2 partitions
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*
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*/
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/* No command line, one static partition */
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#undef CONFIG_JFFS2_CMDLINE
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/*
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#define CONFIG_JFFS2_DEV "nor0"
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#define CONFIG_JFFS2_PART_SIZE 0x00780000
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#define CONFIG_JFFS2_PART_OFFSET 0x00080000
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*/
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#define CONFIG_JFFS2_DEV "nand0"
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#define CONFIG_JFFS2_PART_SIZE 0x00200000
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Note: fake mtd_id used, no linux mtd map file */
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/*
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand"
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#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
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*/
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/* NAND flash support */
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#define CONFIG_MTD_NAND_ECC_JFFS2
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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/* DFBUSY is available on Port C, bit 12; 0 if busy */
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#define NAND_WAIT_READY(nand) \
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while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008));
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#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
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#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
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#define WRITE_NAND(d, adr) \
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do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
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#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
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#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */
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#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */
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#define CE_LO 0x04 /* 1 selects chip (CE low) */
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#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
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#define NAND_DISABLE_CE(nand) \
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nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
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#define NAND_ENABLE_CE(nand) \
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nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
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#define NAND_CTL_CLRALE(nandptr) \
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nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
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#define NAND_CTL_SETALE(nandptr) \
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nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
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#define NAND_CTL_CLRCLE(nandptr) \
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nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
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#define NAND_CTL_SETCLE(nandptr) \
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nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save a little memory */
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#define CFG_PROMPT "=>" /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFF000000
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#define CFG_IMMR_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SRAM_BASE 0xF4000000
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#define CFG_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */
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#define CFG_FLASH_BASE 0xF8000000
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#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
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#define CFG_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */
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#define CFG_DFLASH_SIZE 0x00010000
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#define CFG_FPGA_BASE 0xFF100000 /* Xilinx FPGA */
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#define CFG_FPGA_PROG 0xFF130000 /* Programming address */
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#define CFG_FPGA_SIZE 0x00040000 /* 256KiB usable */
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
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* AMD 29LV641 has 128 64K sectors in 8MB
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*/
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#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* set the PLL, the low-power modes and the reset control (15-29)
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*/
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#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller
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* differently. Normally, you write the option register
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* first, and then enable the chip select by writing the
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* base register. For CS0, you must write the base register
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* first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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*
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**********************************************************
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* BR0 and OR0 (FLASH)
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*/
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#define CFG_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)
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#define CONFIG_FLASH_16BIT
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
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#define CFG_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */
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/**********************************************************
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* BR1 and OR1 (FPGA)
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* These preliminary values are also the final values.
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*/
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#define CFG_OR_TIMING_FPGA \
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(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
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#define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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#define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)
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/**********************************************************
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* BR4 and OR4 (data flash)
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* These preliminary values are also the final values.
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*/
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#define CFG_OR_TIMING_DFLASH \
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(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
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#define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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#define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)
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/**********************************************************
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* BR5/6 and OR5/6 (Dual UART)
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*/
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#define CFG_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */
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#define CFG_DUARTA_BASE 0xff010000
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#define CFG_DUARTB_BASE 0xff018000
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#define DUART_MBMR 0
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#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
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#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
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#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
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#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
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/**********************************************************
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CONFIG_RESET_ON_PANIC /* reset if system panic() */
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#define CFG_ENV_IS_IN_FLASH
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#ifdef CFG_ENV_IS_IN_FLASH
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/* environment is in FLASH */
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#define CFG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */
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#define CFG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */
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#define CFG_ENV_SECT_SIZE 0x00010000
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#define CFG_ENV_SIZE 0x00002000
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#else
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/* environment is in EEPROM */
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_ENV_OFFSET 0 /* at beginning of EEPROM */
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#define CFG_ENV_SIZE 1024 /* Use only a part of it*/
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#endif
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#if 1
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#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
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#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
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#define CONFIG_AUTOBOOT_DELAY_STR "delayabit"
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#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */
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#endif
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#endif /* __CONFIG_H */
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