upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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91 lines
2.7 KiB
91 lines
2.7 KiB
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef DDR2_DIMM_PARAMS_H
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#define DDR2_DIMM_PARAMS_H
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/* Parameters for a DDR2 dimm computed from the SPD */
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typedef struct dimm_params_s {
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/* DIMM organization parameters */
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char mpart[19]; /* guaranteed null terminated */
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unsigned int n_ranks;
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unsigned long long rank_density;
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unsigned long long capacity;
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unsigned int data_width;
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unsigned int primary_sdram_width;
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unsigned int ec_sdram_width;
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unsigned int registered_dimm;
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/* SDRAM device parameters */
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unsigned int n_row_addr;
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unsigned int n_col_addr;
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unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
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unsigned int n_banks_per_sdram_device;
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unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
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unsigned int row_density;
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/* used in computing base address of DIMMs */
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unsigned long long base_address;
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/* mirrored DIMMs */
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unsigned int mirrored_dimm; /* only for ddr3 */
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/* DIMM timing parameters */
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unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
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unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */
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unsigned int tFAW_ps; /* four active window delay, only for ddr3 */
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/*
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* SDRAM clock periods
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* The range for these are 1000-10000 so a short should be sufficient
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*/
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unsigned int tCKmin_X_ps;
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unsigned int tCKmin_X_minus_1_ps;
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unsigned int tCKmin_X_minus_2_ps;
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unsigned int tCKmax_ps;
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/* SPD-defined CAS latencies */
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unsigned int caslat_X;
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unsigned int caslat_X_minus_1;
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unsigned int caslat_X_minus_2;
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unsigned int caslat_lowest_derated; /* Derated CAS latency */
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/* basic timing parameters */
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unsigned int tRCD_ps;
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unsigned int tRP_ps;
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unsigned int tRAS_ps;
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unsigned int tWR_ps; /* maximum = 63750 ps */
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unsigned int tWTR_ps; /* maximum = 63750 ps */
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unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
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= 511750 ps */
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unsigned int tRRD_ps; /* maximum = 63750 ps */
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unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
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unsigned int refresh_rate_ps;
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/* DDR3 doesn't need these as below */
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unsigned int tIS_ps; /* byte 32, spd->ca_setup */
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unsigned int tIH_ps; /* byte 33, spd->ca_hold */
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unsigned int tDS_ps; /* byte 34, spd->data_setup */
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unsigned int tDH_ps; /* byte 35, spd->data_hold */
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unsigned int tRTP_ps; /* byte 38, spd->trtp */
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unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
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unsigned int tQHS_ps; /* byte 45, spd->tqhs */
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} dimm_params_t;
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extern unsigned int ddr_compute_dimm_parameters(
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const generic_spd_eeprom_t *spd,
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dimm_params_t *pdimm,
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unsigned int dimm_number);
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#endif
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