upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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70 lines
2.2 KiB
70 lines
2.2 KiB
/*
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* Configuation settings for the Renesas RSK2+SH7264 board
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*
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* Copyright (C) 2011 Renesas Electronics Europe Ltd.
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008 Renesas Solutions Corp.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __RSK7264_H
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#define __RSK7264_H
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#undef DEBUG
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#define CONFIG_CPU_SH7264 1
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#define CONFIG_RSK7264 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS "console=ttySC3,115200"
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
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#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
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#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
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#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
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#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
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/* Serial */
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#define CONFIG_SCIF_CONSOLE 1
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#define CONFIG_CONS_SCIF3 1
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/* Memory */
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/* u-boot relocated to top 256KB of ram */
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#define CONFIG_SYS_TEXT_BASE 0x0CFC0000
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#define CONFIG_SYS_SDRAM_BASE 0x0C000000
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
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/* Flash */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET (128 * 1024)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 36000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
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#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
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/* Network interface */
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_16_BIT
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#define CONFIG_SMC911X_BASE 0x28000000
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#endif /* __RSK7264_H */
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