upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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418 lines
12 KiB
418 lines
12 KiB
/*
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* Copyright (C) 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright (C) 2009 TechNexion Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __TAM3517_H
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#define __TAM3517_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_OMAP /* in a TI OMAP core */
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#define CONFIG_OMAP_GPIO
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#define CONFIG_OMAP_COMMON
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/* Common ARM Erratas */
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#define CONFIG_ARM_ERRATA_454179
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#define CONFIG_ARM_ERRATA_430973
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#define CONFIG_ARM_ERRATA_621766
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#define CONFIG_SYS_TEXT_BASE 0x80008000
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
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2 * 1024 * 1024)
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/*
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* DDR related
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*/
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#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
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#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
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#define CONFIG_SERIAL1 /* UART1 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DOS_PARTITION
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/* EHCI */
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#define CONFIG_OMAP3_GPIO_5
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_OMAP
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#define CONFIG_USB_ULPI
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#define CONFIG_USB_ULPI_VIEWPORT_OMAP
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#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
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#define CONFIG_USB_STORAGE
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/* commands to include */
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_NAND /* NAND support */
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_EEPROM
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
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#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_OMAP34XX
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access */
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/* nand at CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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/* NAND devices */
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#define CONFIG_AUTO_COMPLETE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 32 /* max number of command */
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/* args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
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/* address */
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/*
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* AM3517 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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#define CONFIG_NAND
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_ENV_IS_IN_NAND
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#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
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/* Redundant Environment */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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2 * CONFIG_SYS_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* ethernet support, EMAC
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*
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*/
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_DRIVER_TI_EMAC_USE_RMII
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#define CONFIG_MII
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#define CONFIG_EMAC_MDIO_PHY_NUM 0
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_CONSOLE
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SPL_POWER_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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/* NAND boot config */
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
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48, 49, 50, 51, 52, 53, 54, 55,\
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56, 57, 58, 59, 60, 61, 62, 63}
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
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#define CONFIG_NAND_OMAP_GPMC_PREFETCH
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
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#define CONFIG_OF_LIBFDT
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#define CONFIG_FIT
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_CMD_MTDPARTS
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/* Setup MTD for NAND on the SOM */
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
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"1m(u-boot),256k(env1)," \
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"256k(env2),6m(kernel),-(rootfs)"
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#define CONFIG_TAM3517_SETTINGS \
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"netdev=eth0\0" \
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"nandargs=setenv bootargs root=${nandroot} " \
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"rootfstype=${nandrootfstype}\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip_sta=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
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"addip=if test -n ${ipdyn};then run addip_dyn;" \
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"else run addip_sta;fi\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"addtty=setenv bootargs ${bootargs}" \
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" console=ttyO0,${baudrate}\0" \
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"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
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"loadaddr=82000000\0" \
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"kernel_addr_r=82000000\0" \
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"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
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"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
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"flash_self=run ramargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr}\0" \
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"nandboot=run nandargs addip addtty addmtd addmisc;" \
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"nand read ${kernel_addr_r} kernel\0" \
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"bootm ${kernel_addr_r}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
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"run nfsargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr_r}\0" \
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"net_self=if run net_self_load;then " \
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"run ramargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
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"else echo Images not loades;fi\0" \
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"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
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"load=tftp ${loadaddr} ${u-boot}\0" \
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"loadmlo=tftp ${loadaddr} ${mlo}\0" \
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"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
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"uboot_addr=0x80000\0" \
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"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
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"nand write ${loadaddr} ${uboot_addr} 80000\0" \
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"updatemlo=nandecc hw;nand erase 0 20000;" \
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"nand write ${loadaddr} 0 20000\0" \
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"upd=if run load;then echo Updating u-boot;if run update;" \
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"then echo U-Boot updated;" \
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"else echo Error updating u-boot !;" \
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"echo Board without bootloader !!;" \
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"fi;" \
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"else echo U-Boot not downloaded..exiting;fi\0" \
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/*
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* this is common code for all TAM3517 boards.
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* MAC address is stored from manufacturer in
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* I2C EEPROM
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*/
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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/*
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* The I2C EEPROM on the TAM3517 contains
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* mac address and production data
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*/
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struct tam3517_module_info {
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char customer[48];
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char product[48];
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/*
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* bit 0~47 : sequence number
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* bit 48~55 : week of year, from 0.
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* bit 56~63 : year
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*/
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unsigned long long sequence_number;
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/*
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* bit 0~7 : revision fixed
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* bit 8~15 : revision major
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* bit 16~31 : TNxxx
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*/
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unsigned int revision;
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unsigned char eth_addr[4][8];
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unsigned char _rev[100];
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};
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#define TAM3517_READ_EEPROM(info, ret) \
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do { \
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
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if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
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(void *)info, sizeof(*info))) \
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ret = 1; \
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else \
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ret = 0; \
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} while (0)
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#define TAM3517_READ_MAC_FROM_EEPROM(info) \
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do { \
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char buf[80], ethname[20]; \
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int i; \
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memset(buf, 0, sizeof(buf)); \
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for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
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sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
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(info)->eth_addr[i][5], \
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(info)->eth_addr[i][4], \
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(info)->eth_addr[i][3], \
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(info)->eth_addr[i][2], \
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(info)->eth_addr[i][1], \
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(info)->eth_addr[i][0]); \
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\
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if (i) \
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sprintf(ethname, "eth%daddr", i); \
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else \
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strcpy(ethname, "ethaddr"); \
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printf("Setting %s from EEPROM with %s\n", ethname, buf);\
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setenv(ethname, buf); \
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} \
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} while (0)
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/* The following macros are taken from Technexion's documentation */
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#define TAM3517_sequence_number(info) \
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((info)->sequence_number % 0x1000000000000LL)
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#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
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#define TAM3517_year(info) ((info)->sequence_number >> 56)
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#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
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#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
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#define TAM3517_revision_tn(info) ((info)->revision >> 16)
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#define TAM3517_PRINT_SOM_INFO(info) \
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do { \
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printf("Vendor:%s\n", (info)->customer); \
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printf("SOM: %s\n", (info)->product); \
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printf("SeqNr: %02llu%02llu%012llu\n", \
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TAM3517_year(info), \
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TAM3517_week_of_year(info), \
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TAM3517_sequence_number(info)); \
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printf("Rev: TN%u %u.%u\n", \
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TAM3517_revision_tn(info), \
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TAM3517_revision_major(info), \
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TAM3517_revision_fixed(info)); \
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} while (0)
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#endif
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#endif /* __TAM3517_H */
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