upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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106 lines
2.6 KiB
106 lines
2.6 KiB
/*
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* GIC Initialization Routines.
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*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/gic.h>
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/*************************************************************************
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*
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* void gic_init(void) __attribute__((weak));
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*
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* Currently, this routine only initialize secure copy of GIC
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* with Security Extensions at EL3.
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*
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*************************************************************************/
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WEAK(gic_init)
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branch_if_slave x0, 2f
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/* Initialize Distributor and SPIs */
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ldr x1, =GICD_BASE
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mov w0, #0x3 /* EnableGrp0 | EnableGrp1 */
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str w0, [x1, GICD_CTLR] /* Secure GICD_CTLR */
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ldr w0, [x1, GICD_TYPER]
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and w2, w0, #0x1f /* ITLinesNumber */
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cbz w2, 2f /* No SPIs */
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add x1, x1, (GICD_IGROUPRn + 4)
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mov w0, #~0 /* Config SPIs as Grp1 */
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1: str w0, [x1], #0x4
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sub w2, w2, #0x1
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cbnz w2, 1b
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/* Initialize SGIs and PPIs */
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2: ldr x1, =GICD_BASE
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mov w0, #~0 /* Config SGIs and PPIs as Grp1 */
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str w0, [x1, GICD_IGROUPRn] /* GICD_IGROUPR0 */
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mov w0, #0x1 /* Enable SGI 0 */
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str w0, [x1, GICD_ISENABLERn]
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/* Initialize Cpu Interface */
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ldr x1, =GICC_BASE
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mov w0, #0x1e7 /* Disable IRQ/FIQ Bypass & */
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/* Enable Ack Group1 Interrupt & */
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/* EnableGrp0 & EnableGrp1 */
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str w0, [x1, GICC_CTLR] /* Secure GICC_CTLR */
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mov w0, #0x1 << 7 /* Non-Secure access to GICC_PMR */
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str w0, [x1, GICC_PMR]
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ret
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ENDPROC(gic_init)
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/*************************************************************************
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*
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* void gic_send_sgi(u64 sgi) __attribute__((weak));
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*
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*************************************************************************/
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WEAK(gic_send_sgi)
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ldr x1, =GICD_BASE
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mov w2, #0x8000
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movk w2, #0x100, lsl #16
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orr w2, w2, w0
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str w2, [x1, GICD_SGIR]
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ret
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ENDPROC(gic_send_sgi)
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/*************************************************************************
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*
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* void wait_for_wakeup(void) __attribute__((weak));
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*
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* Wait for SGI 0 from master.
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*
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*************************************************************************/
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WEAK(wait_for_wakeup)
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ldr x1, =GICC_BASE
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0: wfi
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ldr w0, [x1, GICC_AIAR]
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str w0, [x1, GICC_AEOIR]
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cbnz w0, 0b
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ret
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ENDPROC(wait_for_wakeup)
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/*************************************************************************
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*
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* void smp_kick_all_cpus(void) __attribute__((weak));
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*
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*************************************************************************/
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WEAK(smp_kick_all_cpus)
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/* Kick secondary cpus up by SGI 0 interrupt */
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mov x0, xzr /* SGI 0 */
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mov x29, lr /* Save LR */
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bl gic_send_sgi
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(smp_kick_all_cpus)
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