upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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179 lines
4.5 KiB
179 lines
4.5 KiB
/*
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* (C) Copyright 2006 OpenMoko, Inc.
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* Author: Harald Welte <laforge@openmoko.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if 0
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#define DEBUGN printf
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#else
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#define DEBUGN(x, args ...) {}
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#endif
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#if defined(CONFIG_CMD_NAND)
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#if !defined(CONFIG_NAND_LEGACY)
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#include <nand.h>
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#include <s3c2410.h>
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#include <asm/io.h>
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#define __REGb(x) (*(volatile unsigned char *)(x))
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#define __REGi(x) (*(volatile unsigned int *)(x))
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#define NF_BASE 0x4e000000
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#define NFCONF __REGi(NF_BASE + 0x0)
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#define NFCMD __REGb(NF_BASE + 0x4)
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#define NFADDR __REGb(NF_BASE + 0x8)
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#define NFDATA __REGb(NF_BASE + 0xc)
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#define NFSTAT __REGb(NF_BASE + 0x10)
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#define NFECC0 __REGb(NF_BASE + 0x14)
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#define NFECC1 __REGb(NF_BASE + 0x15)
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#define NFECC2 __REGb(NF_BASE + 0x16)
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_512BYTE (1<<14)
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#define S3C2410_NFCONF_4STEP (1<<13)
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#define S3C2410_NFCONF_INITECC (1<<12)
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#define S3C2410_NFCONF_nFCE (1<<11)
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#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
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#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
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#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
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#define S3C2410_ADDR_NALE 4
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#define S3C2410_ADDR_NCLE 8
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static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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DEBUGN("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
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if (ctrl & NAND_CTRL_CHANGE) {
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ulong IO_ADDR_W = NF_BASE;
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if (!(ctrl & NAND_CLE))
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IO_ADDR_W |= S3C2410_ADDR_NCLE;
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if (!(ctrl & NAND_ALE))
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IO_ADDR_W |= S3C2410_ADDR_NALE;
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chip->IO_ADDR_W = (void *)IO_ADDR_W;
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if (ctrl & NAND_NCE)
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NFCONF &= ~S3C2410_NFCONF_nFCE;
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else
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NFCONF |= S3C2410_NFCONF_nFCE;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, chip->IO_ADDR_W);
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}
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static int s3c2410_dev_ready(struct mtd_info *mtd)
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{
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DEBUGN("dev_ready\n");
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return (NFSTAT & 0x01);
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}
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#ifdef CONFIG_S3C2410_NAND_HWECC
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void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
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NFCONF |= S3C2410_NFCONF_INITECC;
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}
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static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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{
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ecc_code[0] = NFECC0;
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ecc_code[1] = NFECC1;
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ecc_code[2] = NFECC2;
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DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
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mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
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return 0;
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}
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static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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if (read_ecc[0] == calc_ecc[0] &&
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read_ecc[1] == calc_ecc[1] &&
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read_ecc[2] == calc_ecc[2])
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return 0;
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printf("s3c2410_nand_correct_data: not implemented\n");
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return -1;
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}
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#endif
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int board_nand_init(struct nand_chip *nand)
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{
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u_int32_t cfg;
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u_int8_t tacls, twrph0, twrph1;
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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DEBUGN("board_nand_init()\n");
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clk_power->CLKCON |= (1 << 4);
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/* initialize hardware */
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twrph0 = 3; twrph1 = 0; tacls = 0;
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cfg = S3C2410_NFCONF_EN;
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cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
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cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
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NFCONF = cfg;
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/* initialize nand_chip data structure */
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nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e00000c;
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/* read_buf and write_buf are default */
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/* read_byte and write_byte are default */
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/* hwcontrol always must be implemented */
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nand->cmd_ctrl = s3c2410_hwcontrol;
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nand->dev_ready = s3c2410_dev_ready;
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#ifdef CONFIG_S3C2410_NAND_HWECC
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nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
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nand->ecc.calculate = s3c2410_nand_calculate_ecc;
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nand->ecc.correct = s3c2410_nand_correct_data;
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nand->ecc.mode = NAND_ECC_HW3_512;
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#else
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nand->ecc.mode = NAND_ECC_SOFT;
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#endif
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#ifdef CONFIG_S3C2410_NAND_BBT
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nand->options = NAND_USE_FLASH_BBT;
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#else
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nand->options = 0;
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#endif
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DEBUGN("end of nand_init\n");
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return 0;
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}
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#else
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#error "U-Boot legacy NAND support not available for S3C2410"
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#endif
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#endif
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