upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Paul Burton 8755d50706 MIPS: clear TagLo select 2 during cache init ... Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>		10 years ago
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Makefile	MIPS: unify cache initialization code	10 years ago
ashldi3.c	dm: mips: Import libgcc components from Linux	13 years ago
ashrdi3.c	dm: mips: Import libgcc components from Linux	13 years ago
bootm.c	MIPS: bootm: add bootstage reporting	10 years ago
cache.c	MIPS: unify cache maintenance functions	10 years ago
cache_init.S	MIPS: clear TagLo select 2 during cache init	10 years ago
io.c	MIPS: move mips_io_port_base out of board.c	11 years ago
libgcc.h	dm: mips: Import libgcc components from Linux	13 years ago
lshrdi3.c	dm: mips: Import libgcc components from Linux	13 years ago