upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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391 lines
9.9 KiB
391 lines
9.9 KiB
/*
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* Micrel PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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* (C) 2012 NetModule AG, David Andrey, added KSZ9031
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* (C) Copyright 2017 Adaptrum, Inc.
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* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <micrel.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* KSZ9021 - KSZ9031 common
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*/
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#define MII_KSZ90xx_PHY_CTL 0x1f
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#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
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#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
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#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
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#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
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/* KSZ9021 PHY Registers */
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#define MII_KSZ9021_EXTENDED_CTRL 0x0b
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#define MII_KSZ9021_EXTENDED_DATAW 0x0c
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#define MII_KSZ9021_EXTENDED_DATAR 0x0d
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#define CTRL1000_PREFER_MASTER (1 << 10)
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#define CTRL1000_CONFIG_MASTER (1 << 11)
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#define CTRL1000_MANUAL_CONFIG (1 << 12)
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/* KSZ9031 PHY Registers */
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#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
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#define MII_KSZ9031_MMD_REG_DATA 0x0e
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static int ksz90xx_startup(struct phy_device *phydev)
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{
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unsigned phy_ctl;
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
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if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
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phydev->speed = SPEED_1000;
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else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
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phydev->speed = SPEED_100;
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else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
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phydev->speed = SPEED_10;
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return 0;
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}
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/* Common OF config bits for KSZ9021 and KSZ9031 */
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#ifdef CONFIG_DM_ETH
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struct ksz90x1_reg_field {
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const char *name;
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const u8 size; /* Size of the bitfield, in bits */
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const u8 off; /* Offset from bit 0 */
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const u8 dflt; /* Default value */
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};
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struct ksz90x1_ofcfg {
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const u16 reg;
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const u16 devad;
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const struct ksz90x1_reg_field *grp;
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const u16 grpsz;
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};
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static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
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{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
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{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
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};
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static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
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{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
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{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
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};
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static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
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{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
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{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
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};
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static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
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{ "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
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};
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static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
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{ "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
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};
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static int ksz90x1_of_config_group(struct phy_device *phydev,
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struct ksz90x1_ofcfg *ofcfg)
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{
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struct udevice *dev = phydev->dev;
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struct phy_driver *drv = phydev->drv;
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const int ps_to_regval = 60;
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int val[4];
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int i, changed = 0, offset, max;
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u16 regval = 0;
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if (!drv || !drv->writeext)
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return -EOPNOTSUPP;
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for (i = 0; i < ofcfg->grpsz; i++) {
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val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
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offset = ofcfg->grp[i].off;
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if (val[i] == -1) {
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/* Default register value for KSZ9021 */
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regval |= ofcfg->grp[i].dflt << offset;
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} else {
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changed = 1; /* Value was changed in OF */
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/* Calculate the register value and fix corner cases */
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if (val[i] > ps_to_regval * 0xf) {
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max = (1 << ofcfg->grp[i].size) - 1;
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regval |= max << offset;
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} else {
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regval |= (val[i] / ps_to_regval) << offset;
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}
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}
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}
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if (!changed)
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return 0;
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return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
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}
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static int ksz9021_of_config(struct phy_device *phydev)
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{
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struct ksz90x1_ofcfg ofcfg[] = {
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{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
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{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
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{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
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};
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
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ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
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if (ret)
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return ret;
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}
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return 0;
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}
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static int ksz9031_of_config(struct phy_device *phydev)
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{
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struct ksz90x1_ofcfg ofcfg[] = {
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{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
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{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
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{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
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{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
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};
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
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ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
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if (ret)
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return ret;
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}
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return 0;
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}
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static int ksz9031_center_flp_timing(struct phy_device *phydev)
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{
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struct phy_driver *drv = phydev->drv;
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int ret = 0;
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if (!drv || !drv->writeext)
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return -EOPNOTSUPP;
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ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
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if (ret)
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return ret;
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ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
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return ret;
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}
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#else /* !CONFIG_DM_ETH */
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static int ksz9021_of_config(struct phy_device *phydev)
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{
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return 0;
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}
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static int ksz9031_of_config(struct phy_device *phydev)
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{
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return 0;
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}
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static int ksz9031_center_flp_timing(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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/*
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* KSZ9021
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*/
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int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
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{
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/* extended registers */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
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return phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9021_EXTENDED_DATAW, val);
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}
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int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
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{
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/* extended registers */
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phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
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return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
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}
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static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
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int regnum)
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{
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return ksz9021_phy_extended_read(phydev, regnum);
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}
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static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
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int devaddr, int regnum, u16 val)
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{
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return ksz9021_phy_extended_write(phydev, regnum, val);
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}
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static int ksz9021_config(struct phy_device *phydev)
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{
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unsigned ctrl1000 = 0;
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const unsigned master = CTRL1000_PREFER_MASTER |
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CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
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unsigned features = phydev->drv->features;
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int ret;
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ret = ksz9021_of_config(phydev);
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if (ret)
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return ret;
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if (env_get("disable_giga"))
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features &= ~(SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full);
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/* force master mode for 1000BaseT due to chip errata */
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if (features & SUPPORTED_1000baseT_Half)
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ctrl1000 |= ADVERTISE_1000HALF | master;
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if (features & SUPPORTED_1000baseT_Full)
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ctrl1000 |= ADVERTISE_1000FULL | master;
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phydev->advertising = features;
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phydev->supported = features;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
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genphy_config_aneg(phydev);
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genphy_restart_aneg(phydev);
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return 0;
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}
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static struct phy_driver ksz9021_driver = {
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.name = "Micrel ksz9021",
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.uid = 0x221610,
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.mask = 0xfffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &ksz9021_config,
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.startup = &ksz90xx_startup,
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.shutdown = &genphy_shutdown,
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.writeext = &ksz9021_phy_extwrite,
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.readext = &ksz9021_phy_extread,
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};
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/*
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* KSZ9031
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*/
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int ksz9031_phy_extended_write(struct phy_device *phydev,
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int devaddr, int regnum, u16 mode, u16 val)
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{
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/*select register addr for mmd*/
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
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/*select register for mmd*/
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_REG_DATA, regnum);
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/*setup mode*/
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
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/*write the value*/
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return phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_REG_DATA, val);
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}
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int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
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int regnum, u16 mode)
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{
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_REG_DATA, regnum);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
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return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
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}
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static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
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int regnum)
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{
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return ksz9031_phy_extended_read(phydev, devaddr, regnum,
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MII_KSZ9031_MOD_DATA_NO_POST_INC);
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}
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static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
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int devaddr, int regnum, u16 val)
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{
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return ksz9031_phy_extended_write(phydev, devaddr, regnum,
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MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
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}
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static int ksz9031_config(struct phy_device *phydev)
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{
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int ret;
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ret = ksz9031_of_config(phydev);
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if (ret)
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return ret;
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ret = ksz9031_center_flp_timing(phydev);
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if (ret)
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return ret;
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/* add an option to disable the gigabit feature of this PHY */
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if (env_get("disable_giga")) {
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unsigned features;
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unsigned bmcr;
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/* disable speed 1000 in features supported by the PHY */
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features = phydev->drv->features;
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features &= ~(SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full);
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phydev->advertising = phydev->supported = features;
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/* disable speed 1000 in Basic Control Register */
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bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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bmcr &= ~(1 << 6);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
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/* disable speed 1000 in 1000Base-T Control Register */
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
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/* start autoneg */
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genphy_config_aneg(phydev);
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genphy_restart_aneg(phydev);
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return 0;
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}
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return genphy_config(phydev);
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}
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static struct phy_driver ksz9031_driver = {
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.name = "Micrel ksz9031",
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.uid = 0x221620,
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.mask = 0xfffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &ksz9031_config,
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.startup = &ksz90xx_startup,
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.shutdown = &genphy_shutdown,
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.writeext = &ksz9031_phy_extwrite,
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.readext = &ksz9031_phy_extread,
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};
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int phy_micrel_ksz90x1_init(void)
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{
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phy_register(&ksz9021_driver);
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phy_register(&ksz9031_driver);
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return 0;
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}
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