upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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443 lines
12 KiB
443 lines
12 KiB
/*
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* Vitesse PHY drivers
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*
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* Copyright 2010-2014 Freescale Semiconductor, Inc.
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* Original Author: Andy Fleming
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* Add vsc8662 phy support - Priyanka Jain
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <miiphy.h>
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/* Cicada Auxiliary Control/Status Register */
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#define MIIM_CIS82xx_AUX_CONSTAT 0x1c
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#define MIIM_CIS82xx_AUXCONSTAT_INIT 0x0004
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#define MIIM_CIS82xx_AUXCONSTAT_DUPLEX 0x0020
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#define MIIM_CIS82xx_AUXCONSTAT_SPEED 0x0018
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#define MIIM_CIS82xx_AUXCONSTAT_GBIT 0x0010
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#define MIIM_CIS82xx_AUXCONSTAT_100 0x0008
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/* Cicada Extended Control Register 1 */
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#define MIIM_CIS82xx_EXT_CON1 0x17
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#define MIIM_CIS8201_EXTCON1_INIT 0x0000
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/* Cicada 8204 Extended PHY Control Register 1 */
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#define MIIM_CIS8204_EPHY_CON 0x17
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#define MIIM_CIS8204_EPHYCON_INIT 0x0006
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#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
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/* Cicada 8204 Serial LED Control Register */
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#define MIIM_CIS8204_SLED_CON 0x1b
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#define MIIM_CIS8204_SLEDCON_INIT 0x1115
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/* Vitesse VSC8601 Extended PHY Control Register 1 */
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#define MII_VSC8601_EPHY_CTL 0x17
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#define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
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#define PHY_EXT_PAGE_ACCESS 0x1f
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#define PHY_EXT_PAGE_ACCESS_GENERAL 0x10
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#define PHY_EXT_PAGE_ACCESS_EXTENDED3 0x3
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/* Vitesse VSC8574 control register */
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#define MIIM_VSC8574_MAC_SERDES_CON 0x10
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#define MIIM_VSC8574_MAC_SERDES_ANEG 0x80
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#define MIIM_VSC8574_GENERAL18 0x12
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#define MIIM_VSC8574_GENERAL19 0x13
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/* Vitesse VSC8574 gerenal purpose register 18 */
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#define MIIM_VSC8574_18G_SGMII 0x80f0
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#define MIIM_VSC8574_18G_QSGMII 0x80e0
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#define MIIM_VSC8574_18G_CMDSTAT 0x8000
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/* Vitesse VSC8514 control register */
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#define MIIM_VSC8514_MAC_SERDES_CON 0x10
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#define MIIM_VSC8514_GENERAL18 0x12
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#define MIIM_VSC8514_GENERAL19 0x13
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#define MIIM_VSC8514_GENERAL23 0x17
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/* Vitesse VSC8514 gerenal purpose register 18 */
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#define MIIM_VSC8514_18G_QSGMII 0x80e0
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#define MIIM_VSC8514_18G_CMDSTAT 0x8000
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/* Vitesse VSC8664 Control/Status Register */
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#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13
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#define MIIM_VSC8664_ADDITIONAL_DEV 0x16
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#define MIIM_VSC8664_EPHY_CON 0x17
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#define MIIM_VSC8664_LED_CON 0x1E
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#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001
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/* CIS8201 */
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static int vitesse_config(struct phy_device *phydev)
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{
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/* Override PHY config settings */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
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MIIM_CIS82xx_AUXCONSTAT_INIT);
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/* Set up the interface mode */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1,
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MIIM_CIS8201_EXTCON1_INIT);
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genphy_config_aneg(phydev);
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return 0;
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}
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static int vitesse_parse_status(struct phy_device *phydev)
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{
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int speed;
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int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT);
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if (mii_reg & MIIM_CIS82xx_AUXCONSTAT_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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speed = mii_reg & MIIM_CIS82xx_AUXCONSTAT_SPEED;
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switch (speed) {
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case MIIM_CIS82xx_AUXCONSTAT_GBIT:
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phydev->speed = SPEED_1000;
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break;
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case MIIM_CIS82xx_AUXCONSTAT_100:
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phydev->speed = SPEED_100;
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break;
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default:
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phydev->speed = SPEED_10;
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break;
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}
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return 0;
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}
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static int vitesse_startup(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return vitesse_parse_status(phydev);
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}
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static int cis8204_config(struct phy_device *phydev)
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{
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/* Override PHY config settings */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
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MIIM_CIS82xx_AUXCONSTAT_INIT);
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genphy_config_aneg(phydev);
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if (phy_interface_is_rgmii(phydev))
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
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MIIM_CIS8204_EPHYCON_INIT |
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MIIM_CIS8204_EPHYCON_RGMII);
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else
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
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MIIM_CIS8204_EPHYCON_INIT);
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return 0;
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}
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/* Vitesse VSC8601 */
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/* This adds a skew for both TX and RX clocks, so the skew should only be
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* applied to "rgmii-id" interfaces. It may not work as expected
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* on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
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static int vsc8601_add_skew(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL);
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if (ret < 0)
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return ret;
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ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
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return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret);
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}
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static int vsc8601_config(struct phy_device *phydev)
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{
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int ret = 0;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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ret = vsc8601_add_skew(phydev);
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if (ret < 0)
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return ret;
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return genphy_config_aneg(phydev);
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}
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static int vsc8574_config(struct phy_device *phydev)
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{
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u32 val;
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/* configure register 19G for MAC */
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
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PHY_EXT_PAGE_ACCESS_GENERAL);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19);
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if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
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/* set bit 15:14 to '01' for QSGMII mode */
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val = (val & 0x3fff) | (1 << 14);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_VSC8574_GENERAL19, val);
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/* Enable 4 ports MAC QSGMII */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
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MIIM_VSC8574_18G_QSGMII);
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} else {
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/* set bit 15:14 to '00' for SGMII mode */
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val = val & 0x3fff;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val);
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/* Enable 4 ports MAC SGMII */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
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MIIM_VSC8574_18G_SGMII);
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}
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
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/* When bit 15 is cleared the command has completed */
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while (val & MIIM_VSC8574_18G_CMDSTAT)
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
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/* Enable Serdes Auto-negotiation */
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
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PHY_EXT_PAGE_ACCESS_EXTENDED3);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON);
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val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val);
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
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genphy_config_aneg(phydev);
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return 0;
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}
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static int vsc8514_config(struct phy_device *phydev)
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{
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u32 val;
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int timeout = 1000000;
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/* configure register to access 19G */
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
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PHY_EXT_PAGE_ACCESS_GENERAL);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19);
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if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
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/* set bit 15:14 to '01' for QSGMII mode */
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val = (val & 0x3fff) | (1 << 14);
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_VSC8514_GENERAL19, val);
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/* Enable 4 ports MAC QSGMII */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18,
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MIIM_VSC8514_18G_QSGMII);
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} else {
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/*TODO Add SGMII functionality once spec sheet
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* for VSC8514 defines complete functionality
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*/
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}
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
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/* When bit 15 is cleared the command has completed */
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while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--)
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
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if (0 == timeout) {
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printf("PHY 8514 config failed\n");
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return -1;
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}
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
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/* configure register to access 23 */
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23);
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/* set bits 10:8 to '000' */
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val = (val & 0xf8ff);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val);
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/* Enable Serdes Auto-negotiation */
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
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PHY_EXT_PAGE_ACCESS_EXTENDED3);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON);
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val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val);
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
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genphy_config_aneg(phydev);
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return 0;
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}
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static int vsc8664_config(struct phy_device *phydev)
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{
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u32 val;
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/* Enable MAC interface auto-negotiation */
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
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val |= (1 << 13);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
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PHY_EXT_PAGE_ACCESS_EXTENDED);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
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val |= (1 << 11);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
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phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
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/* Enable LED blink */
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
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val &= ~(1 << 2);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
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genphy_config_aneg(phydev);
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return 0;
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}
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static struct phy_driver VSC8211_driver = {
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.name = "Vitesse VSC8211",
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.uid = 0xfc4b0,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &vitesse_config,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8221_driver = {
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.name = "Vitesse VSC8221",
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.uid = 0xfc550,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &genphy_config_aneg,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8244_driver = {
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.name = "Vitesse VSC8244",
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.uid = 0xfc6c0,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &genphy_config_aneg,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8234_driver = {
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.name = "Vitesse VSC8234",
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.uid = 0xfc620,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &genphy_config_aneg,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8574_driver = {
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.name = "Vitesse VSC8574",
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.uid = 0x704a0,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &vsc8574_config,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8514_driver = {
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.name = "Vitesse VSC8514",
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.uid = 0x70670,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &vsc8514_config,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8584_driver = {
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.name = "Vitesse VSC8584",
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.uid = 0x707c0,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &vsc8574_config,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8601_driver = {
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.name = "Vitesse VSC8601",
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.uid = 0x70420,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &vsc8601_config,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8641_driver = {
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.name = "Vitesse VSC8641",
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.uid = 0x70430,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &genphy_config_aneg,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8662_driver = {
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.name = "Vitesse VSC8662",
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.uid = 0x70660,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &genphy_config_aneg,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver VSC8664_driver = {
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.name = "Vitesse VSC8664",
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.uid = 0x70660,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &vsc8664_config,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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/* Vitesse bought Cicada, so we'll put these here */
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static struct phy_driver cis8201_driver = {
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.name = "CIS8201",
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.uid = 0xfc410,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &vitesse_config,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver cis8204_driver = {
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.name = "Cicada Cis8204",
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.uid = 0xfc440,
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.mask = 0xffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &cis8204_config,
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.startup = &vitesse_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_vitesse_init(void)
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{
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phy_register(&VSC8641_driver);
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phy_register(&VSC8601_driver);
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phy_register(&VSC8234_driver);
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phy_register(&VSC8244_driver);
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phy_register(&VSC8211_driver);
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phy_register(&VSC8221_driver);
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phy_register(&VSC8574_driver);
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phy_register(&VSC8584_driver);
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phy_register(&VSC8514_driver);
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phy_register(&VSC8662_driver);
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phy_register(&VSC8664_driver);
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phy_register(&cis8201_driver);
|
|
phy_register(&cis8204_driver);
|
|
|
|
return 0;
|
|
}
|
|
|