upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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519 lines
14 KiB
519 lines
14 KiB
/*
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* (C) Copyright 2010
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* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
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*
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* (C) Copyright 2012
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* Amit Virdi, ST Microelectronics, amit.virdi@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/fsmc_nand.h>
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#include <asm/arch/hardware.h>
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static u32 fsmc_version;
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static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *)
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CONFIG_SYS_FSMC_BASE;
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/*
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* ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
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* data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can
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* correct 1 bit in 512 bytes
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*/
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static struct nand_ecclayout fsmc_ecc4_lp_layout = {
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.eccbytes = 104,
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.eccpos = { 2, 3, 4, 5, 6, 7, 8,
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9, 10, 11, 12, 13, 14,
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18, 19, 20, 21, 22, 23, 24,
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25, 26, 27, 28, 29, 30,
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34, 35, 36, 37, 38, 39, 40,
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41, 42, 43, 44, 45, 46,
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50, 51, 52, 53, 54, 55, 56,
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57, 58, 59, 60, 61, 62,
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66, 67, 68, 69, 70, 71, 72,
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73, 74, 75, 76, 77, 78,
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82, 83, 84, 85, 86, 87, 88,
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89, 90, 91, 92, 93, 94,
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98, 99, 100, 101, 102, 103, 104,
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105, 106, 107, 108, 109, 110,
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114, 115, 116, 117, 118, 119, 120,
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121, 122, 123, 124, 125, 126
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},
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.oobfree = {
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{.offset = 15, .length = 3},
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{.offset = 31, .length = 3},
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{.offset = 47, .length = 3},
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{.offset = 63, .length = 3},
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{.offset = 79, .length = 3},
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{.offset = 95, .length = 3},
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{.offset = 111, .length = 3},
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{.offset = 127, .length = 1}
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}
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};
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/*
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* ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
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* of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
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* bytes are free for use.
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*/
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static struct nand_ecclayout fsmc_ecc4_224_layout = {
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.eccbytes = 104,
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.eccpos = { 2, 3, 4, 5, 6, 7, 8,
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9, 10, 11, 12, 13, 14,
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18, 19, 20, 21, 22, 23, 24,
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25, 26, 27, 28, 29, 30,
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34, 35, 36, 37, 38, 39, 40,
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41, 42, 43, 44, 45, 46,
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50, 51, 52, 53, 54, 55, 56,
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57, 58, 59, 60, 61, 62,
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66, 67, 68, 69, 70, 71, 72,
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73, 74, 75, 76, 77, 78,
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82, 83, 84, 85, 86, 87, 88,
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89, 90, 91, 92, 93, 94,
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98, 99, 100, 101, 102, 103, 104,
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105, 106, 107, 108, 109, 110,
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114, 115, 116, 117, 118, 119, 120,
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121, 122, 123, 124, 125, 126
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},
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.oobfree = {
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{.offset = 15, .length = 3},
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{.offset = 31, .length = 3},
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{.offset = 47, .length = 3},
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{.offset = 63, .length = 3},
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{.offset = 79, .length = 3},
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{.offset = 95, .length = 3},
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{.offset = 111, .length = 3},
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{.offset = 127, .length = 97}
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}
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};
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/*
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* ECC placement definitions in oobfree type format
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* There are 13 bytes of ecc for every 512 byte block and it has to be read
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* consecutively and immediately after the 512 byte data block for hardware to
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* generate the error bit offsets in 512 byte data
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* Managing the ecc bytes in the following way makes it easier for software to
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* read ecc bytes consecutive to data bytes. This way is similar to
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* oobfree structure maintained already in u-boot nand driver
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*/
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static struct fsmc_eccplace fsmc_eccpl_lp = {
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.eccplace = {
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{.offset = 2, .length = 13},
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{.offset = 18, .length = 13},
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{.offset = 34, .length = 13},
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{.offset = 50, .length = 13},
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{.offset = 66, .length = 13},
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{.offset = 82, .length = 13},
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{.offset = 98, .length = 13},
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{.offset = 114, .length = 13}
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}
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};
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static struct nand_ecclayout fsmc_ecc4_sp_layout = {
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.eccbytes = 13,
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.eccpos = { 0, 1, 2, 3, 6, 7, 8,
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9, 10, 11, 12, 13, 14
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},
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.oobfree = {
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{.offset = 15, .length = 1},
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}
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};
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static struct fsmc_eccplace fsmc_eccpl_sp = {
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.eccplace = {
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{.offset = 0, .length = 4},
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{.offset = 6, .length = 9}
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}
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};
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static struct nand_ecclayout fsmc_ecc1_layout = {
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.eccbytes = 24,
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.eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
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66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
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.oobfree = {
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{.offset = 8, .length = 8},
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{.offset = 24, .length = 8},
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{.offset = 40, .length = 8},
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{.offset = 56, .length = 8},
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{.offset = 72, .length = 8},
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{.offset = 88, .length = 8},
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{.offset = 104, .length = 8},
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{.offset = 120, .length = 8}
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}
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};
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/* Count the number of 0's in buff upto a max of max_bits */
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static int count_written_bits(uint8_t *buff, int size, int max_bits)
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{
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int k, written_bits = 0;
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for (k = 0; k < size; k++) {
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written_bits += hweight8(~buff[k]);
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if (written_bits > max_bits)
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break;
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}
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return written_bits;
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}
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static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
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{
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struct nand_chip *this = mtd_to_nand(mtd);
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ulong IO_ADDR_W;
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if (ctrl & NAND_CTRL_CHANGE) {
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IO_ADDR_W = (ulong)this->IO_ADDR_W;
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IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
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if (ctrl & NAND_NCE) {
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writel(readl(&fsmc_regs_p->pc) |
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FSMC_ENABLE, &fsmc_regs_p->pc);
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} else {
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writel(readl(&fsmc_regs_p->pc) &
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~FSMC_ENABLE, &fsmc_regs_p->pc);
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}
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this->IO_ADDR_W = (void *)IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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/* The calculated ecc is actually the correction index in data */
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u32 err_idx[8];
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u32 num_err, i;
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u32 ecc1, ecc2, ecc3, ecc4;
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num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF;
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if (likely(num_err == 0))
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return 0;
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if (unlikely(num_err > 8)) {
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/*
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* This is a temporary erase check. A newly erased page read
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* would result in an ecc error because the oob data is also
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* erased to FF and the calculated ecc for an FF data is not
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* FF..FF.
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* This is a workaround to skip performing correction in case
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* data is FF..FF
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*
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* Logic:
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* For every page, each bit written as 0 is counted until these
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* number of bits are greater than 8 (the maximum correction
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* capability of FSMC for each 512 + 13 bytes)
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*/
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int bits_ecc = count_written_bits(read_ecc, 13, 8);
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int bits_data = count_written_bits(dat, 512, 8);
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if ((bits_ecc + bits_data) <= 8) {
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if (bits_data)
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memset(dat, 0xff, 512);
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return bits_data + bits_ecc;
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}
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return -EBADMSG;
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}
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ecc1 = readl(&fsmc_regs_p->ecc1);
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ecc2 = readl(&fsmc_regs_p->ecc2);
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ecc3 = readl(&fsmc_regs_p->ecc3);
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ecc4 = readl(&fsmc_regs_p->sts);
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err_idx[0] = (ecc1 >> 0) & 0x1FFF;
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err_idx[1] = (ecc1 >> 13) & 0x1FFF;
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err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
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err_idx[3] = (ecc2 >> 7) & 0x1FFF;
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err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
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err_idx[5] = (ecc3 >> 1) & 0x1FFF;
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err_idx[6] = (ecc3 >> 14) & 0x1FFF;
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err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
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i = 0;
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while (i < num_err) {
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err_idx[i] ^= 3;
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if (err_idx[i] < 512 * 8)
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__change_bit(err_idx[i], dat);
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i++;
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}
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return num_err;
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}
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static int fsmc_read_hwecc(struct mtd_info *mtd,
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const u_char *data, u_char *ecc)
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{
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u_int ecc_tmp;
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int timeout = CONFIG_SYS_HZ;
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ulong start;
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switch (fsmc_version) {
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case FSMC_VER8:
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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/*
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* Busy waiting for ecc computation
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* to finish for 512 bytes
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*/
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if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY)
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break;
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}
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ecc_tmp = readl(&fsmc_regs_p->ecc1);
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ecc[0] = (u_char) (ecc_tmp >> 0);
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ecc[1] = (u_char) (ecc_tmp >> 8);
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ecc[2] = (u_char) (ecc_tmp >> 16);
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ecc[3] = (u_char) (ecc_tmp >> 24);
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ecc_tmp = readl(&fsmc_regs_p->ecc2);
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ecc[4] = (u_char) (ecc_tmp >> 0);
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ecc[5] = (u_char) (ecc_tmp >> 8);
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ecc[6] = (u_char) (ecc_tmp >> 16);
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ecc[7] = (u_char) (ecc_tmp >> 24);
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ecc_tmp = readl(&fsmc_regs_p->ecc3);
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ecc[8] = (u_char) (ecc_tmp >> 0);
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ecc[9] = (u_char) (ecc_tmp >> 8);
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ecc[10] = (u_char) (ecc_tmp >> 16);
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ecc[11] = (u_char) (ecc_tmp >> 24);
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ecc_tmp = readl(&fsmc_regs_p->sts);
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ecc[12] = (u_char) (ecc_tmp >> 16);
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break;
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default:
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ecc_tmp = readl(&fsmc_regs_p->ecc1);
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ecc[0] = (u_char) (ecc_tmp >> 0);
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ecc[1] = (u_char) (ecc_tmp >> 8);
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ecc[2] = (u_char) (ecc_tmp >> 16);
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break;
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}
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return 0;
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}
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void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256,
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&fsmc_regs_p->pc);
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writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN,
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&fsmc_regs_p->pc);
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writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN,
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&fsmc_regs_p->pc);
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}
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/*
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* fsmc_read_page_hwecc
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* @mtd: mtd info structure
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* @chip: nand chip info structure
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* @buf: buffer to store read data
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* @oob_required: caller expects OOB data read to chip->oob_poi
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* @page: page number to read
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*
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* This routine is needed for fsmc verison 8 as reading from NAND chip has to be
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* performed in a strict sequence as follows:
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* data(512 byte) -> ecc(13 byte)
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* After this read, fsmc hardware generates and reports error data bits(upto a
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* max of 8 bits)
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*/
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static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int oob_required, int page)
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{
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struct fsmc_eccplace *fsmc_eccpl;
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int i, j, s, stat, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint8_t *p = buf;
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uint8_t *ecc_calc = chip->buffers->ecccalc;
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uint8_t *ecc_code = chip->buffers->ecccode;
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int off, len, group = 0;
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uint8_t oob[13] __attribute__ ((aligned (2)));
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/* Differentiate between small and large page ecc place definitions */
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if (mtd->writesize == 512)
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fsmc_eccpl = &fsmc_eccpl_sp;
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else
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fsmc_eccpl = &fsmc_eccpl_lp;
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for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
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chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
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chip->ecc.hwctl(mtd, NAND_ECC_READ);
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chip->read_buf(mtd, p, eccsize);
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for (j = 0; j < eccbytes;) {
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off = fsmc_eccpl->eccplace[group].offset;
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len = fsmc_eccpl->eccplace[group].length;
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group++;
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/*
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* length is intentionally kept a higher multiple of 2
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* to read at least 13 bytes even in case of 16 bit NAND
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* devices
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*/
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if (chip->options & NAND_BUSWIDTH_16)
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len = roundup(len, 2);
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chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
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chip->read_buf(mtd, oob + j, len);
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j += len;
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}
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memcpy(&ecc_code[i], oob, 13);
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chip->ecc.calculate(mtd, p, &ecc_calc[i]);
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stat = chip->ecc.correct(mtd, p, &ecc_code[i],
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&ecc_calc[i]);
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if (stat < 0)
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += stat;
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}
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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/*
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* fsmc_nand_switch_ecc - switch the ECC operation between different engines
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*
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* @eccstrength - the number of bits that could be corrected
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* (1 - HW, 4 - SW BCH4)
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*/
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int fsmc_nand_switch_ecc(uint32_t eccstrength)
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{
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struct nand_chip *nand;
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struct mtd_info *mtd;
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int err;
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/*
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* This functions is only called on SPEAr600 platforms, supporting
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* 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
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* Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
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* function, as it doesn't need to switch to a different ECC layout.
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*/
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mtd = get_nand_dev_by_index(nand_curr_device);
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nand = mtd_to_nand(mtd);
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/* Setup the ecc configurations again */
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if (eccstrength == 1) {
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.bytes = 3;
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nand->ecc.strength = 1;
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nand->ecc.layout = &fsmc_ecc1_layout;
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nand->ecc.calculate = fsmc_read_hwecc;
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nand->ecc.correct = nand_correct_data;
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} else if (eccstrength == 4) {
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/*
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* .calculate .correct and .bytes will be set in
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* nand_scan_tail()
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*/
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nand->ecc.mode = NAND_ECC_SOFT_BCH;
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nand->ecc.strength = 4;
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nand->ecc.layout = NULL;
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} else {
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printf("Error: ECC strength %d not supported!\n", eccstrength);
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}
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/* Update NAND handling after ECC mode switch */
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err = nand_scan_tail(mtd);
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return err;
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}
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#endif /* CONFIG_SPL_BUILD */
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int fsmc_nand_init(struct nand_chip *nand)
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{
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static int chip_nr;
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struct mtd_info *mtd;
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u32 peripid2 = readl(&fsmc_regs_p->peripid2);
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fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
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FSMC_REVISION_MSK;
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writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl);
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#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
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writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
|
|
&fsmc_regs_p->pc);
|
|
#elif defined(CONFIG_SYS_FSMC_NAND_8BIT)
|
|
writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
|
|
&fsmc_regs_p->pc);
|
|
#else
|
|
#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT
|
|
#endif
|
|
writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1,
|
|
&fsmc_regs_p->pc);
|
|
writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
|
|
&fsmc_regs_p->comm);
|
|
writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
|
|
&fsmc_regs_p->attrib);
|
|
|
|
nand->options = 0;
|
|
#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
|
|
nand->options |= NAND_BUSWIDTH_16;
|
|
#endif
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.size = 512;
|
|
nand->ecc.calculate = fsmc_read_hwecc;
|
|
nand->ecc.hwctl = fsmc_enable_hwecc;
|
|
nand->cmd_ctrl = fsmc_nand_hwcontrol;
|
|
nand->IO_ADDR_R = nand->IO_ADDR_W =
|
|
(void __iomem *)CONFIG_SYS_NAND_BASE;
|
|
nand->badblockbits = 7;
|
|
|
|
mtd = nand_to_mtd(nand);
|
|
|
|
switch (fsmc_version) {
|
|
case FSMC_VER8:
|
|
nand->ecc.bytes = 13;
|
|
nand->ecc.strength = 8;
|
|
nand->ecc.correct = fsmc_bch8_correct_data;
|
|
nand->ecc.read_page = fsmc_read_page_hwecc;
|
|
if (mtd->writesize == 512)
|
|
nand->ecc.layout = &fsmc_ecc4_sp_layout;
|
|
else {
|
|
if (mtd->oobsize == 224)
|
|
nand->ecc.layout = &fsmc_ecc4_224_layout;
|
|
else
|
|
nand->ecc.layout = &fsmc_ecc4_lp_layout;
|
|
}
|
|
|
|
break;
|
|
default:
|
|
nand->ecc.bytes = 3;
|
|
nand->ecc.strength = 1;
|
|
nand->ecc.layout = &fsmc_ecc1_layout;
|
|
nand->ecc.correct = nand_correct_data;
|
|
break;
|
|
}
|
|
|
|
/* Detect NAND chips */
|
|
if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
|
|
return -ENXIO;
|
|
|
|
if (nand_scan_tail(mtd))
|
|
return -ENXIO;
|
|
|
|
if (nand_register(chip_nr++, mtd))
|
|
return -ENXIO;
|
|
|
|
return 0;
|
|
}
|
|
|