upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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185 lines
5.8 KiB
185 lines
5.8 KiB
/*
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* SH7751 PCI Controller (PCIC) for U-Boot.
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* (C) Dustin McIntire (dustin@sensoria.com)
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* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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/* Register addresses and such */
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#define SH7751_BCR1 (vu_long *)0xFF800000
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#define SH7751_BCR2 (vu_short *)0xFF800004
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#define SH7751_WCR1 (vu_long *)0xFF800008
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#define SH7751_WCR2 (vu_long *)0xFF80000C
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#define SH7751_WCR3 (vu_long *)0xFF800010
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#define SH7751_MCR (vu_long *)0xFF800014
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#define SH7751_BCR3 (vu_short *)0xFF800050
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#define SH7751_PCICONF0 (vu_long *)0xFE200000
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#define SH7751_PCICONF1 (vu_long *)0xFE200004
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#define SH7751_PCICONF2 (vu_long *)0xFE200008
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#define SH7751_PCICONF3 (vu_long *)0xFE20000C
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#define SH7751_PCICONF4 (vu_long *)0xFE200010
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#define SH7751_PCICONF5 (vu_long *)0xFE200014
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#define SH7751_PCICONF6 (vu_long *)0xFE200018
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#define SH7751_PCICR (vu_long *)0xFE200100
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#define SH7751_PCILSR0 (vu_long *)0xFE200104
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#define SH7751_PCILSR1 (vu_long *)0xFE200108
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#define SH7751_PCILAR0 (vu_long *)0xFE20010C
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#define SH7751_PCILAR1 (vu_long *)0xFE200110
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#define SH7751_PCIMBR (vu_long *)0xFE2001C4
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#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
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#define SH7751_PCIPINT (vu_long *)0xFE2001CC
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#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
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#define SH7751_PCICLKR (vu_long *)0xFE2001D4
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#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
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#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
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#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
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#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
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#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
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#define SH7751_PCIMCR (vu_long *)0xFE2001F4
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#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
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#define BCR1_BREQEN 0x00080000
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#define PCI_SH7751_ID 0x35051054
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#define PCI_SH7751R_ID 0x350E1054
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#define SH7751_PCICONF1_WCC 0x00000080
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#define SH7751_PCICONF1_PER 0x00000040
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#define SH7751_PCICONF1_BUM 0x00000004
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#define SH7751_PCICONF1_MES 0x00000002
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#define SH7751_PCICONF1_CMDS 0x000000C6
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#define SH7751_PCI_HOST_BRIDGE 0x6
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#define SH7751_PCICR_PREFIX 0xa5000000
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#define SH7751_PCICR_PRST 0x00000002
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#define SH7751_PCICR_CFIN 0x00000001
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#define SH7751_PCIPINT_D3 0x00000002
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#define SH7751_PCIPINT_D0 0x00000001
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#define SH7751_PCICLKR_PREFIX 0xa5000000
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#define SH7751_PCI_MEM_BASE 0xFD000000
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#define SH7751_PCI_MEM_SIZE 0x01000000
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#define SH7751_PCI_IO_BASE 0xFE240000
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#define SH7751_PCI_IO_SIZE 0x00040000
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#define SH7751_PCIPAR (vu_long *)0xFE2001C0
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#define SH7751_PCIPDR (vu_long *)0xFE200220
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#define p4_in(addr) (*addr)
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#define p4_out(data, addr) (*addr) = (data)
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/* Double word */
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int pci_sh4_read_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 *value)
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{
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u32 par_data = 0x80000000 | dev;
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p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
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*value = p4_in(SH7751_PCIPDR);
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return 0;
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}
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int pci_sh4_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 value)
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{
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u32 par_data = 0x80000000 | dev;
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p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
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p4_out(value, SH7751_PCIPDR);
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return 0;
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}
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int pci_sh7751_init(struct pci_controller *hose)
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{
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/* Double-check that we're a 7751 or 7751R chip */
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if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
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&& p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
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printf("PCI: Unknown PCI host bridge.\n");
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return 1;
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}
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printf("PCI: SH7751 PCI host bridge found.\n");
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/* Double-check some BSC config settings */
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/* (Area 3 non-MPX 32-bit, PCI bus pins) */
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if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
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printf("SH7751_BCR1 value is wrong(0x%08X)\n",
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(unsigned int)p4_in(SH7751_BCR1));
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return 2;
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}
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if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
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printf("SH7751_BCR2 value is wrong(0x%08X)\n",
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(unsigned int)p4_in(SH7751_BCR2));
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return 3;
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}
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if (p4_in(SH7751_BCR2) & 0x01) {
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printf("SH7751_BCR2 value is wrong(0x%08X)\n",
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(unsigned int)p4_in(SH7751_BCR2));
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return 4;
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}
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/* Force BREQEN in BCR1 to allow PCIC access */
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p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
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/* Toggle PCI reset pin */
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p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
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udelay(32);
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p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
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/* Set cmd bits: WCC, PER, BUM, MES */
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/* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
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p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
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/* Define this host as the host bridge */
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p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
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/* Force PCI clock(s) on */
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p4_out(0, SH7751_PCICLKR);
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p4_out(0x03, SH7751_PCICLKR);
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/* Clear powerdown IRQs, also mask them (unused) */
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p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
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p4_out(0, SH7751_PCIPINTM);
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p4_out(0xab000001, SH7751_PCICONF4);
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/* Set up target memory mappings (for external DMA access) */
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/* Map both P0 and P2 range to Area 3 RAM for ease of use */
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p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
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p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
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p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
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p4_out(0, SH7751_PCILSR1);
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p4_out(0, SH7751_PCILAR1);
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p4_out(0xd0000000, SH7751_PCICONF6);
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/* Map memory window to same address on PCI bus */
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p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
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/* Map IO window to same address on PCI bus */
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p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
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/* set BREQEN */
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p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
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/* Copy BSC registers into PCI BSC */
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p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
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p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
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p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
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p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
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p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
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p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
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p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
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/* Finally, set central function init complete */
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p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
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pci_sh4_init(hose);
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return 0;
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}
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