upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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294 lines
7.6 KiB
294 lines
7.6 KiB
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/grf_rk322x.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/periph.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rk322x_pinctrl_priv {
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struct rk322x_grf *grf;
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};
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static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
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{
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u32 mux_con = readl(&grf->con_iomux);
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switch (pwm_id) {
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case PERIPH_ID_PWM0:
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if (mux_con & CON_IOMUX_PWM0SEL_MASK)
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rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
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GPIO3C5_PWM10 << GPIO3C5_SHIFT);
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else
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rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
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GPIO0D2_PWM0 << GPIO0D2_SHIFT);
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break;
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case PERIPH_ID_PWM1:
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if (mux_con & CON_IOMUX_PWM1SEL_MASK)
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rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
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GPIO0D6_PWM11 << GPIO0D6_SHIFT);
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else
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rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
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GPIO0D3_PWM1 << GPIO0D3_SHIFT);
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break;
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case PERIPH_ID_PWM2:
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if (mux_con & CON_IOMUX_PWM2SEL_MASK)
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rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
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GPIO1B4_PWM12 << GPIO1B4_SHIFT);
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else
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rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
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GPIO0D4_PWM2 << GPIO0D4_SHIFT);
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break;
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case PERIPH_ID_PWM3:
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if (mux_con & CON_IOMUX_PWM3SEL_MASK)
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rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
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GPIO1B3_PWM13 << GPIO1B3_SHIFT);
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else
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rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
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GPIO3D2_PWM3 << GPIO3D2_SHIFT);
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break;
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default:
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debug("pwm id = %d iomux error!\n", pwm_id);
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break;
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}
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}
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static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
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{
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switch (i2c_id) {
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case PERIPH_ID_I2C0:
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rk_clrsetreg(&grf->gpio0a_iomux,
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GPIO0A1_MASK | GPIO0A0_MASK,
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GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
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GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
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break;
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case PERIPH_ID_I2C1:
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rk_clrsetreg(&grf->gpio0a_iomux,
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GPIO0A3_MASK | GPIO0A2_MASK,
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GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
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GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
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break;
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case PERIPH_ID_I2C2:
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rk_clrsetreg(&grf->gpio2c_iomux,
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GPIO2C5_MASK | GPIO2C4_MASK,
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GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
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GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
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break;
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case PERIPH_ID_I2C3:
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rk_clrsetreg(&grf->gpio0a_iomux,
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GPIO0A7_MASK | GPIO0A6_MASK,
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GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
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GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
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break;
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}
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}
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static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
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{
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switch (cs) {
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case 0:
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rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
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GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
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break;
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case 1:
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rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
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GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
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break;
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}
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rk_clrsetreg(&grf->gpio0b_iomux,
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GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
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GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
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GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
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GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
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}
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static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
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{
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u32 mux_con = readl(&grf->con_iomux);
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switch (uart_id) {
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case PERIPH_ID_UART1:
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if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK | GPIO1B2_MASK,
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GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
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GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
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break;
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case PERIPH_ID_UART2:
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if (mux_con & CON_IOMUX_UART2SEL_MASK)
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK | GPIO1B2_MASK,
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GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
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GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
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else
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rk_clrsetreg(&grf->gpio1c_iomux,
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GPIO1C3_MASK | GPIO1C2_MASK,
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GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
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GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
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break;
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}
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}
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static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
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{
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switch (mmc_id) {
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case PERIPH_ID_EMMC:
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rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
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GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
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GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
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GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
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GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
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GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
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GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
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GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
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GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A5_MASK | GPIO2A7_MASK,
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GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
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GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
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rk_clrsetreg(&grf->gpio1c_iomux,
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GPIO1C6_MASK | GPIO1C7_MASK,
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GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
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GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
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break;
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case PERIPH_ID_SDCARD:
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B6_MASK | GPIO1B7_MASK,
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GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
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GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT);
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rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
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GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
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GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
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GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
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GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
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GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
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GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
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break;
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}
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}
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static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
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{
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struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
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debug("%s: func=%x, flags=%x\n", __func__, func, flags);
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switch (func) {
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case PERIPH_ID_PWM0:
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case PERIPH_ID_PWM1:
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case PERIPH_ID_PWM2:
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case PERIPH_ID_PWM3:
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pinctrl_rk322x_pwm_config(priv->grf, func);
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break;
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case PERIPH_ID_I2C0:
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case PERIPH_ID_I2C1:
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case PERIPH_ID_I2C2:
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pinctrl_rk322x_i2c_config(priv->grf, func);
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break;
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case PERIPH_ID_SPI0:
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pinctrl_rk322x_spi_config(priv->grf, flags);
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break;
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART2:
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pinctrl_rk322x_uart_config(priv->grf, func);
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break;
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case PERIPH_ID_SDMMC0:
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case PERIPH_ID_SDMMC1:
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pinctrl_rk322x_sdmmc_config(priv->grf, func);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
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struct udevice *periph)
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{
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u32 cell[3];
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int ret;
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ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
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"interrupts", cell, ARRAY_SIZE(cell));
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if (ret < 0)
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return -EINVAL;
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switch (cell[1]) {
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case 12:
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return PERIPH_ID_SDCARD;
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case 14:
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return PERIPH_ID_EMMC;
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case 36:
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return PERIPH_ID_I2C0;
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case 37:
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return PERIPH_ID_I2C1;
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case 38:
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return PERIPH_ID_I2C2;
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case 49:
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return PERIPH_ID_SPI0;
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case 50:
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return PERIPH_ID_PWM0;
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case 55:
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return PERIPH_ID_UART0;
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case 56:
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return PERIPH_ID_UART1;
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case 57:
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return PERIPH_ID_UART2;
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}
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return -ENOENT;
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}
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static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
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struct udevice *periph)
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{
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int func;
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func = rk322x_pinctrl_get_periph_id(dev, periph);
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if (func < 0)
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return func;
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return rk322x_pinctrl_request(dev, func, 0);
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}
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static struct pinctrl_ops rk322x_pinctrl_ops = {
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.set_state_simple = rk322x_pinctrl_set_state_simple,
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.request = rk322x_pinctrl_request,
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.get_periph_id = rk322x_pinctrl_get_periph_id,
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};
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static int rk322x_pinctrl_probe(struct udevice *dev)
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{
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struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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debug("%s: grf=%p\n", __func__, priv->grf);
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return 0;
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}
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static const struct udevice_id rk322x_pinctrl_ids[] = {
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{ .compatible = "rockchip,rk322x-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk322x) = {
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.name = "pinctrl_rk322x",
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.id = UCLASS_PINCTRL,
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.of_match = rk322x_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
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.ops = &rk322x_pinctrl_ops,
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.bind = dm_scan_fdt_dev,
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.probe = rk322x_pinctrl_probe,
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};
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