upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.4 KiB
149 lines
3.4 KiB
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk3368.h>
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#include <asm/arch/periph.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rk3368_pinctrl_priv {
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struct rk3368_grf *grf;
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struct rk3368_pmu_grf *pmugrf;
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};
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static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
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int uart_id)
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{
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struct rk3368_grf *grf = priv->grf;
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struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
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switch (uart_id) {
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case PERIPH_ID_UART2:
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A6_MASK | GPIO2A5_MASK,
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GPIO2A6_UART2_SIN << GPIO2A6_SHIFT |
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GPIO2A5_UART2_SOUT << GPIO2A5_SHIFT);
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break;
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case PERIPH_ID_UART0:
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break;
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case PERIPH_ID_UART1:
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break;
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case PERIPH_ID_UART3:
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break;
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case PERIPH_ID_UART4:
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rk_clrsetreg(&pmugrf->gpio0d_iomux,
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GPIO0D0_MASK | GPIO0D1_MASK |
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GPIO0D2_MASK | GPIO0D3_MASK,
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GPIO0D0_GPIO << GPIO0D0_SHIFT |
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GPIO0D1_GPIO << GPIO0D1_SHIFT |
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GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
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GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
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break;
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default:
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debug("uart id = %d iomux error!\n", uart_id);
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break;
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}
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}
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static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
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{
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struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
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debug("%s: func=%d, flags=%x\n", __func__, func, flags);
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switch (func) {
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART2:
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case PERIPH_ID_UART3:
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case PERIPH_ID_UART4:
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pinctrl_rk3368_uart_config(priv, func);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
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struct udevice *periph)
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{
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u32 cell[3];
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int ret;
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ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
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"interrupts", cell, ARRAY_SIZE(cell));
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if (ret < 0)
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return -EINVAL;
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switch (cell[1]) {
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case 59:
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return PERIPH_ID_UART4;
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case 58:
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return PERIPH_ID_UART3;
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case 57:
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return PERIPH_ID_UART2;
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case 56:
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return PERIPH_ID_UART1;
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case 55:
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return PERIPH_ID_UART0;
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}
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return -ENOENT;
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}
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static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
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struct udevice *periph)
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{
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int func;
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func = rk3368_pinctrl_get_periph_id(dev, periph);
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if (func < 0)
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return func;
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return rk3368_pinctrl_request(dev, func, 0);
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}
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static struct pinctrl_ops rk3368_pinctrl_ops = {
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.set_state_simple = rk3368_pinctrl_set_state_simple,
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.request = rk3368_pinctrl_request,
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.get_periph_id = rk3368_pinctrl_get_periph_id,
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};
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static int rk3368_pinctrl_probe(struct udevice *dev)
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{
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struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
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int ret = 0;
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
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debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
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return ret;
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}
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static const struct udevice_id rk3368_pinctrl_ids[] = {
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{ .compatible = "rockchip,rk3368-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3368) = {
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.name = "rockchip_rk3368_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3368_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
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.ops = &rk3368_pinctrl_ops,
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.bind = dm_scan_fdt_dev,
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.probe = rk3368_pinctrl_probe,
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};
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