upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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201 lines
7.0 KiB
201 lines
7.0 KiB
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/*------------------------------------------------------*/
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/* TERON Articia / SDRAM Init */
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/*------------------------------------------------------*/
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* XD_CTL = 0x81000000 (0x74)
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* HBUS_ACC_CTL_0 &= 0xFFFFFDFF (0x5c)
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/* host bus access ctl reg 2(5e) */
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/* set - CPU read from memory data one clock after data is latched */
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* GLOBL_INFO_0 |= 0x00004000 (0x50)
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/* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
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PCI_1_SB_CONFIG_0 |= 0x00000400 (0x80d0)
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/* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
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MEM_RAS_CTL_0 |= 0x3f000000 (0xcc)
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&= 0x3fffffff
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/* RAS park control reg 0(cc), park access enable is set */
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HOST_RDBUF_CTL |= 0x10000000 (0x70)
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&= 0x10ffffff
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/* host read buffer control reg, enable prefetch for CPU read from DRAM control */
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HBUS_ACC_CTL_0 |= 0x0100001f (0x5c)
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&= 0xf1ffffff
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/* host bus access control register, enable CPU address bus pipe control */
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/* two outstanding requests, *** changed to 2 from 3 */
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/* enable line merge write control for CPU write to system memory, PCI 1 */
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/* and PCI 0 bus memory; enable page merge write control for write to */
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/* PCI bus 0 & bus 1 memory */
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SRAM_CTL |= 0x00004000 (0xc8)
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&= 0xffbff7ff
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/* DRAM detail timing control register 1 (ca), bit 3 set to 0 */
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/* DRAM start access latency control - wait for one clock */
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/* ff9f changed to ffbf */
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DIM0_TIM_CTL_0 = 0x737d737d (0xc9)
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/* DRAM timing control for dimm0 & dimm1; set wait one clock */
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/* cycle for next data access */
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DIM2_TIM_CTL_0 = 0x737d737d (0xca)
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/* DRAM timing control for dimm2 & dimm3; set wait one clock */
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/* cycle for next data access */
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DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90)
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/* set dimm0 bank0 for 128 MB */
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DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB (0x94)
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/* set dimm0 for bank1 */
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DIM0_TIM_CTL_0 = 0xf3bf0000 (0xc9)
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/* dimm0 timing control register; RAS - CAS latency - 4 clock */
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/* CAS access latency - 3 wait; pre-charge latency - 3 wait */
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/* pre-charge command period control - 5 clock; wait one clock */
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/* cycle for next data access; read to write access latency control */
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/* - 2 clock cycles */
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DRAM_GBL_CTL_0 |= 0x00000100 (0xc0)
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&= 0xffff01ff
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/* memory global control register - support buffer sdram on bank 0 */
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DRAM_ECC_CTL_0 |= 0x00260000 (0xc4)
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&= 0xff26ffff
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/* enable ECC; enable read, modify, write control */
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DRAM_REF_CTL_0 = DRAM_REF_DATA (0xb8)
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/* set DRAM refresh parameters *** changed to 00940100 */
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nop
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nop
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nop
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nop
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nop
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DRAM_ECC_CTL_0 |= 0x20243280 (0xc4)
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/* turn off ecc */
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/* for SDRAM bank 0 */
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DRAM_ECC_CTL_0 |= 0x20243290 (0xc4) ?
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/* for SDRAM bank 1 */
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/* Additional Stuff...*/
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GLOBL_CTRL |= 0x20000b00 (0x54)
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PCI_0_SB_CONFIG |= 0x04100007 (0xd0)
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/* PCI 0 Side band config reg*/
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0x8000083c |= 0x00080000
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/* Disable VGA decode on PCI Bus 1 */
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/*End Additional Stuff..*/
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/*--------------------------------------------------------------*/
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/* TERON serial port initialization code */
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/*--------------------------------------------------------------*/
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0x84380080 |= 0x00030000
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/* enable super IO configuration VIA chip Register 85 */
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/* Enable super I/O config mode */
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0xfe0003f0 = 0xe2
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bl delay1
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0xfe0003f1 = 0x0f
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bl delay1
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/* enable com1 & com2, parallel port disabled */
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0xfe0003f0 = 0xe7
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bl delay1
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/* let's make com1 base as 0x3f8 */
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0xfe0003f1 = 0xfe
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bl delay1
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0xfe0003f0 = 0xe8
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bl delay1
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/* let's make com2 base as 0x2f8 */
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0xfe0003f1 = 0xbe
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0x84380080 &= 0xfffdffff
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/* closing super IO configuration VIA chip Register 85 */
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/* -------------------------------*/
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0xfe0003fb = 0x83
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bl delay1
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/*latch enable word length -8 bit */ /* set mslab bit */
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0xfe0003f8 = 0x0c
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bl delay1
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/* set baud rate lsb for 9600 baud */
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0xfe0003f9 = 0x0
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bl delay1
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/* set baud rate msb for 9600 baud */
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0xfe0003fb = 0x03
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bl delay1
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/* reset mslab */
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/*--------------------------------------------------------------*/
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/* END TERON Serial Port Initialization Code */
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/*--------------------------------------------------------------*/
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/*--------------------------------------------------------------*/
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/* END TERON Articia / SDRAM Initialization code */
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/*--------------------------------------------------------------*/
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Proposed from Documentation:
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write dmem 0xfec00cf8 0x50000080
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write dmem 0xfee00cfc 0xc0305411
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Writes to index 0x50-0x53.
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0x50: Global Information Register 0
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0xC0 = Little Endian CPU, Sequential order Burst
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0x51: Global Information Register 1
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Read only, 0x30 = Provides PowerPC and X86 support
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0x52: Global Information Register 2
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0x05 = 64/128 bit CPU bus support
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0x53: Global Information Register 3
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0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
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write dmem 0xfec00cf8 0x5c000080
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write dmem 0xfee00cfc 0xb300011F
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write dmem 0xfec00cf8 0xc8000080
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write dmem 0xfee00cfc 0x0020f100
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write dmem 0xfec00cf8 0x90000080
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write dmem 0xfee00cfc 0x007fe700
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write dmem 0xfec00cf8 0x9400080
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write dmem 0xfee00cfc 0x007fe700
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write dmem 0xfec00cf8 0xb0000080
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write dmem 0xfee00cfc 0x737d737d
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write dmem 0xfec00cf8 0xb4000080
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write dmem 0xfee00cfc 0x737d737d
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write dmem 0xfec00cf8 0xc0000080
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write dmem 0xfee00cfc 0x40005500
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write dmem 0xfec00cf8 0xb8000080
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write dmem 0xfee00cfc 0x00940100
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write dmem 0xfec00cf8 0xc4000080
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write dmem 0xfee00cfc 0x00003280
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write dmem 0xfec00cf8 0xc4000080
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write dmem 0xfee00cfc 0x00003290
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