upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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947 lines
23 KiB
947 lines
23 KiB
/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*
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* TODO: clean-up
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*/
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#include <common.h>
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#include "pip405.h"
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#include <asm/processor.h>
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#include <i2c.h>
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#include "../common/isa.h"
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#include "../common/common_util.h"
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#undef SDRAM_DEBUG
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#define FALSE 0
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#define TRUE 1
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/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
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#ifndef __ldiv_t_defined
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typedef struct {
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long int quot; /* Quotient */
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long int rem; /* Remainder */
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} ldiv_t;
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extern ldiv_t ldiv (long int __numer, long int __denom);
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# define __ldiv_t_defined 1
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#endif
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typedef enum {
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SDRAM_NO_ERR,
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SDRAM_SPD_COMM_ERR,
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SDRAM_SPD_CHKSUM_ERR,
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SDRAM_UNSUPPORTED_ERR,
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SDRAM_UNKNOWN_ERR
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} SDRAM_ERR;
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typedef struct {
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const unsigned char mode;
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const unsigned char row;
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const unsigned char col;
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const unsigned char bank;
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} SDRAM_SETUP;
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static const SDRAM_SETUP sdram_setup_table[] = {
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{1, 11, 9, 2},
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{1, 11, 10, 2},
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{2, 12, 9, 4},
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{2, 12, 10, 4},
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{3, 13, 9, 4},
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{3, 13, 10, 4},
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{3, 13, 11, 4},
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{4, 12, 8, 2},
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{4, 12, 8, 4},
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{5, 11, 8, 2},
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{5, 11, 8, 4},
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{6, 13, 8, 2},
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{6, 13, 8, 4},
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{7, 13, 9, 2},
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{7, 13, 10, 2},
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{0, 0, 0, 0}
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};
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static const unsigned char cal_indextable[] = {
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9, 23, 25
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};
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/*
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* translate ns.ns/10 coding of SPD timing values
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* into 10 ps unit values
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*/
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unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
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{
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unsigned short ns, ns10;
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/* isolate upper nibble */
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ns = (spd_byte >> 4) & 0x0F;
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/* isolate lower nibble */
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ns10 = (spd_byte & 0x0F);
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return (ns * 100 + ns10 * 10);
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}
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/*
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* translate ns.ns/4 coding of SPD timing values
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* into 10 ps unit values
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*/
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unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
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{
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unsigned short ns, ns4;
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/* isolate upper 6 bits */
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ns = (spd_byte >> 2) & 0x3F;
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/* isloate lower 2 bits */
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ns4 = (spd_byte & 0x03);
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return (ns * 100 + ns4 * 25);
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}
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/*
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* translate ns coding of SPD timing values
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* into 10 ps unit values
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*/
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unsigned short NSto10PS (unsigned char spd_byte)
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{
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return (spd_byte * 100);
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}
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void SDRAM_err (const char *s)
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{
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#ifndef SDRAM_DEBUG
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DECLARE_GLOBAL_DATA_PTR;
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(void) get_clocks ();
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gd->baudrate = 9600;
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serial_init ();
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#endif
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serial_puts ("\n");
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serial_puts (s);
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serial_puts ("\n enable SDRAM_DEBUG for more info\n");
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for (;;);
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}
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#ifdef SDRAM_DEBUG
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void write_hex (unsigned char i)
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{
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char cc;
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cc = i >> 4;
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cc &= 0xf;
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if (cc > 9)
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serial_putc (cc + 55);
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else
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serial_putc (cc + 48);
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cc = i & 0xf;
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if (cc > 9)
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serial_putc (cc + 55);
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else
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serial_putc (cc + 48);
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}
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void write_4hex (unsigned long val)
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{
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write_hex ((unsigned char) (val >> 24));
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write_hex ((unsigned char) (val >> 16));
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write_hex ((unsigned char) (val >> 8));
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write_hex ((unsigned char) val);
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}
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#endif
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int board_pre_init (void)
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{
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unsigned char dataout[1];
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unsigned char datain[128];
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unsigned long sdram_size;
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SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
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unsigned long memclk;
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unsigned long tmemclk = 0;
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unsigned long tmp, bank, baseaddr, bank_size;
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unsigned short i;
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unsigned char rows, cols, banks, sdram_banks, density;
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unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
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trc_clocks, tctp_clocks;
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unsigned char cal_index, cal_val, spd_version, spd_chksum;
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unsigned char buf[8];
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#ifdef SDRAM_DEBUG
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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memclk = get_bus_freq (tmemclk);
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tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
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#ifdef SDRAM_DEBUG
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(void) get_clocks ();
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gd->baudrate = 9600;
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serial_init ();
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serial_puts ("\nstart SDRAM Setup\n");
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#endif
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/* Read Serial Presence Detect Information */
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i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
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dataout[0] = 0;
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for (i = 0; i < 128; i++)
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datain[i] = 127;
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i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
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#ifdef SDRAM_DEBUG
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serial_puts ("\ni2c_read returns ");
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write_hex (i);
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serial_puts ("\n");
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#endif
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#ifdef SDRAM_DEBUG
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for (i = 0; i < 128; i++) {
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write_hex (datain[i]);
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serial_puts (" ");
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if (((i + 1) % 16) == 0)
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serial_puts ("\n");
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}
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serial_puts ("\n");
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#endif
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spd_chksum = 0;
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for (i = 0; i < 63; i++) {
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spd_chksum += datain[i];
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} /* endfor */
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if (datain[63] != spd_chksum) {
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#ifdef SDRAM_DEBUG
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serial_puts ("SPD chksum: 0x");
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write_hex (datain[63]);
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serial_puts (" != calc. chksum: 0x");
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write_hex (spd_chksum);
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serial_puts ("\n");
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#endif
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SDRAM_err ("SPD checksum Error");
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}
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/* SPD seems to be ok, use it */
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/* get SPD version */
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spd_version = datain[62];
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/* do some sanity checks on the kind of RAM */
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if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
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(datain[2] != 0x04) || /* if not SDRAM */
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(!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
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(datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
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(datain[126] == 0x66)) /* or a 66Mhz modules */
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SDRAM_err ("unsupported SDRAM");
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#ifdef SDRAM_DEBUG
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serial_puts ("SDRAM sanity ok\n");
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#endif
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/* get number of rows/cols/banks out of byte 3+4+5 */
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rows = datain[3];
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cols = datain[4];
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banks = datain[5];
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/* get number of SDRAM banks out of byte 17 and
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supported CAS latencies out of byte 18 */
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sdram_banks = datain[17];
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supported_cal = datain[18] & ~0x81;
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while (t->mode != 0) {
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if ((t->row == rows) && (t->col == cols)
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&& (t->bank == sdram_banks))
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break;
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t++;
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} /* endwhile */
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#ifdef SDRAM_DEBUG
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serial_puts ("rows: ");
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write_hex (rows);
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serial_puts (" cols: ");
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write_hex (cols);
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serial_puts (" banks: ");
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write_hex (banks);
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serial_puts (" mode: ");
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write_hex (t->mode);
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serial_puts ("\n");
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#endif
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if (t->mode == 0)
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SDRAM_err ("unsupported SDRAM");
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/* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
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#ifdef SDRAM_DEBUG
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serial_puts ("tRP: ");
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write_hex (datain[27]);
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serial_puts ("\ntRCD: ");
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write_hex (datain[29]);
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serial_puts ("\ntRAS: ");
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write_hex (datain[30]);
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serial_puts ("\n");
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#endif
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trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
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trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
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tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
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density = datain[31];
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/* trc_clocks is sum of trp_clocks + tras_clocks */
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trc_clocks = trp_clocks + tras_clocks;
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/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
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tctp_clocks =
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((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
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(tmemclk - 1)) / tmemclk;
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#ifdef SDRAM_DEBUG
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serial_puts ("c_RP: ");
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write_hex (trp_clocks);
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serial_puts ("\nc_RCD: ");
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write_hex (trcd_clocks);
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serial_puts ("\nc_RAS: ");
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write_hex (tras_clocks);
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serial_puts ("\nc_RC: (RP+RAS): ");
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write_hex (trc_clocks);
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serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
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write_hex (tctp_clocks);
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serial_puts ("\nt_CTP: RAS - RCD: ");
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write_hex ((unsigned
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char) ((NSto10PS (datain[30]) -
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NSto10PS (datain[29])) >> 8));
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write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
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serial_puts ("\ntmemclk: ");
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write_hex ((unsigned char) (tmemclk >> 8));
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write_hex ((unsigned char) (tmemclk));
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serial_puts ("\n");
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#endif
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cal_val = 255;
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for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
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/* is this CAS latency supported ? */
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if ((supported_cal >> i) & 0x01) {
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buf[0] = datain[cal_indextable[cal_index]];
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if (cal_index < 2) {
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if (NS10to10PS (buf[0], spd_version) <= tmemclk)
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cal_val = i;
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} else {
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/* SPD bytes 25+26 have another format */
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if (NS4to10PS (buf[0], spd_version) <= tmemclk)
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cal_val = i;
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} /* endif */
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cal_index++;
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} /* endif */
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} /* endfor */
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#ifdef SDRAM_DEBUG
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serial_puts ("CAL: ");
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write_hex (cal_val + 1);
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serial_puts ("\n");
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#endif
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if (cal_val == 255)
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SDRAM_err ("unsupported SDRAM");
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/* get SDRAM timing register */
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mtdcr (memcfga, mem_sdtr1);
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tmp = mfdcr (memcfgd) & ~0x018FC01F;
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/* insert CASL value */
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/* tmp |= ((unsigned long)cal_val) << 23; */
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tmp |= ((unsigned long) cal_val) << 23;
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/* insert PTA value */
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tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
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/* insert CTP value */
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/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
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tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
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/* insert LDF (always 01) */
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tmp |= ((unsigned long) 0x01) << 14;
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/* insert RFTA value */
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tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
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/* insert RCD value */
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tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
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#ifdef SDRAM_DEBUG
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serial_puts ("sdtr: ");
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write_4hex (tmp);
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serial_puts ("\n");
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#endif
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/* write SDRAM timing register */
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mtdcr (memcfga, mem_sdtr1);
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mtdcr (memcfgd, tmp);
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baseaddr = CFG_SDRAM_BASE;
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bank_size = (((unsigned long) density) << 22) / 2;
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/* insert AM value */
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tmp = ((unsigned long) t->mode - 1) << 13;
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/* insert SZ value; */
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switch (bank_size) {
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case 0x00400000:
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tmp |= ((unsigned long) 0x00) << 17;
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break;
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case 0x00800000:
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tmp |= ((unsigned long) 0x01) << 17;
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break;
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case 0x01000000:
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tmp |= ((unsigned long) 0x02) << 17;
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break;
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case 0x02000000:
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tmp |= ((unsigned long) 0x03) << 17;
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break;
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case 0x04000000:
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tmp |= ((unsigned long) 0x04) << 17;
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break;
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case 0x08000000:
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tmp |= ((unsigned long) 0x05) << 17;
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break;
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case 0x10000000:
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tmp |= ((unsigned long) 0x06) << 17;
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break;
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default:
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SDRAM_err ("unsupported SDRAM");
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} /* endswitch */
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/* get SDRAM bank 0 register */
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mtdcr (memcfga, mem_mb0cf);
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bank = mfdcr (memcfgd) & ~0xFFCEE001;
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bank |= (baseaddr | tmp | 0x01);
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|
#ifdef SDRAM_DEBUG
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serial_puts ("bank0: baseaddr: ");
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write_4hex (baseaddr);
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serial_puts (" banksize: ");
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write_4hex (bank_size);
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serial_puts (" mb0cf: ");
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write_4hex (bank);
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serial_puts ("\n");
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#endif
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baseaddr += bank_size;
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sdram_size += bank_size;
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|
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/* write SDRAM bank 0 register */
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mtdcr (memcfga, mem_mb0cf);
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mtdcr (memcfgd, bank);
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|
|
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/* get SDRAM bank 1 register */
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mtdcr (memcfga, mem_mb1cf);
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bank = mfdcr (memcfgd) & ~0xFFCEE001;
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sdram_size = 0;
|
|
|
|
#ifdef SDRAM_DEBUG
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|
serial_puts ("bank1: baseaddr: ");
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write_4hex (baseaddr);
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serial_puts (" banksize: ");
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write_4hex (bank_size);
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#endif
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if (banks == 2) {
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bank |= (baseaddr | tmp | 0x01);
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baseaddr += bank_size;
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sdram_size += bank_size;
|
|
} /* endif */
|
|
#ifdef SDRAM_DEBUG
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serial_puts (" mb1cf: ");
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write_4hex (bank);
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serial_puts ("\n");
|
|
#endif
|
|
/* write SDRAM bank 1 register */
|
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mtdcr (memcfga, mem_mb1cf);
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|
mtdcr (memcfgd, bank);
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|
|
|
/* get SDRAM bank 2 register */
|
|
mtdcr (memcfga, mem_mb2cf);
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|
bank = mfdcr (memcfgd) & ~0xFFCEE001;
|
|
|
|
bank |= (baseaddr | tmp | 0x01);
|
|
|
|
#ifdef SDRAM_DEBUG
|
|
serial_puts ("bank2: baseaddr: ");
|
|
write_4hex (baseaddr);
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|
serial_puts (" banksize: ");
|
|
write_4hex (bank_size);
|
|
serial_puts (" mb2cf: ");
|
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write_4hex (bank);
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serial_puts ("\n");
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#endif
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baseaddr += bank_size;
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sdram_size += bank_size;
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|
|
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/* write SDRAM bank 2 register */
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|
mtdcr (memcfga, mem_mb2cf);
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mtdcr (memcfgd, bank);
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|
|
|
/* get SDRAM bank 3 register */
|
|
mtdcr (memcfga, mem_mb3cf);
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|
bank = mfdcr (memcfgd) & ~0xFFCEE001;
|
|
|
|
#ifdef SDRAM_DEBUG
|
|
serial_puts ("bank3: baseaddr: ");
|
|
write_4hex (baseaddr);
|
|
serial_puts (" banksize: ");
|
|
write_4hex (bank_size);
|
|
#endif
|
|
|
|
if (banks == 2) {
|
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bank |= (baseaddr | tmp | 0x01);
|
|
baseaddr += bank_size;
|
|
sdram_size += bank_size;
|
|
}
|
|
/* endif */
|
|
#ifdef SDRAM_DEBUG
|
|
serial_puts (" mb3cf: ");
|
|
write_4hex (bank);
|
|
serial_puts ("\n");
|
|
#endif
|
|
|
|
/* write SDRAM bank 3 register */
|
|
mtdcr (memcfga, mem_mb3cf);
|
|
mtdcr (memcfgd, bank);
|
|
|
|
|
|
/* get SDRAM refresh interval register */
|
|
mtdcr (memcfga, mem_rtr);
|
|
tmp = mfdcr (memcfgd) & ~0x3FF80000;
|
|
|
|
if (tmemclk < NSto10PS (16))
|
|
tmp |= 0x05F00000;
|
|
else
|
|
tmp |= 0x03F80000;
|
|
|
|
/* write SDRAM refresh interval register */
|
|
mtdcr (memcfga, mem_rtr);
|
|
mtdcr (memcfgd, tmp);
|
|
|
|
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
|
|
mtdcr (memcfga, mem_mcopt1);
|
|
tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
|
|
mtdcr (memcfga, mem_mcopt1);
|
|
mtdcr (memcfgd, tmp);
|
|
|
|
|
|
|
|
/*-------------------------------------------------------------------------+
|
|
| Interrupt controller setup for the PIP405 board.
|
|
| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
|
|
| IRQ 16 405GP internally generated; active low; level sensitive
|
|
| IRQ 17-24 RESERVED
|
|
| IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
|
|
| IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
|
|
| IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
|
|
| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
|
|
| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
|
|
| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
|
|
| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
|
|
| Note for PIP405 board:
|
|
| An interrupt taken for the SouthBridge (IRQ 25) indicates that
|
|
| the Interrupt Controller in the South Bridge has caused the
|
|
| interrupt. The IC must be read to determine which device
|
|
| caused the interrupt.
|
|
|
|
|
+-------------------------------------------------------------------------*/
|
|
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
|
|
mtdcr (uicer, 0x00000000); /* disable all ints */
|
|
mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
|
|
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
|
|
mtdcr (uictr, 0x10000000); /* set int trigger levels */
|
|
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
|
|
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
/*
|
|
* Check Board Identity:
|
|
*/
|
|
|
|
int checkboard (void)
|
|
{
|
|
unsigned char s[50];
|
|
unsigned char bc;
|
|
int i;
|
|
backup_t *b = (backup_t *) s;
|
|
|
|
puts ("Board: ");
|
|
|
|
i = getenv_r ("serial#", s, 32);
|
|
if ((i == 0) || strncmp (s, "PIP405", 6)) {
|
|
get_backup_values (b);
|
|
if (strncmp (b->signature, "MPL\0", 4) != 0) {
|
|
puts ("### No HW ID - assuming PIP405");
|
|
} else {
|
|
b->serial_name[6] = 0;
|
|
printf ("%s SN: %s", b->serial_name,
|
|
&b->serial_name[7]);
|
|
}
|
|
} else {
|
|
s[6] = 0;
|
|
printf ("%s SN: %s", s, &s[7]);
|
|
}
|
|
bc = in8 (CONFIG_PORT_ADDR);
|
|
printf (" Boot Config: 0x%x\n", bc);
|
|
return (0);
|
|
}
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
/* ------------------------------------------------------------------------- */
|
|
/*
|
|
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
|
|
the necessary info for SDRAM controller configuration
|
|
*/
|
|
/* ------------------------------------------------------------------------- */
|
|
/* ------------------------------------------------------------------------- */
|
|
static int test_dram (unsigned long ramsize);
|
|
|
|
long int initdram (int board_type)
|
|
{
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
unsigned long bank_reg[4], tmp, bank_size;
|
|
int i, ds;
|
|
unsigned long TotalSize;
|
|
|
|
ds = 0;
|
|
/* since the DRAM controller is allready set up,
|
|
* calculate the size with the bank registers
|
|
*/
|
|
mtdcr (memcfga, mem_mb0cf);
|
|
bank_reg[0] = mfdcr (memcfgd);
|
|
mtdcr (memcfga, mem_mb1cf);
|
|
bank_reg[1] = mfdcr (memcfgd);
|
|
mtdcr (memcfga, mem_mb2cf);
|
|
bank_reg[2] = mfdcr (memcfgd);
|
|
mtdcr (memcfga, mem_mb3cf);
|
|
bank_reg[3] = mfdcr (memcfgd);
|
|
TotalSize = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
if ((bank_reg[i] & 0x1) == 0x1) {
|
|
tmp = (bank_reg[i] >> 17) & 0x7;
|
|
bank_size = 4 << tmp;
|
|
TotalSize += bank_size;
|
|
} else
|
|
ds = 1;
|
|
}
|
|
if (ds == 1)
|
|
printf ("single-sided DIMM ");
|
|
else
|
|
printf ("double-sided DIMM ");
|
|
test_dram (TotalSize * 1024 * 1024);
|
|
/* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
|
|
(void) get_clocks();
|
|
if (gd->cpu_clk > 220000000)
|
|
TotalSize /= 2;
|
|
return (TotalSize * 1024 * 1024);
|
|
}
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
|
|
static int test_dram (unsigned long ramsize)
|
|
{
|
|
/* not yet implemented */
|
|
return (1);
|
|
}
|
|
|
|
|
|
int misc_init_r (void)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
/***************************************************************************
|
|
* some helping routines
|
|
*/
|
|
|
|
int overwrite_console (void)
|
|
{
|
|
return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */
|
|
}
|
|
|
|
|
|
|
|
extern int isa_init (void);
|
|
|
|
|
|
void print_pip405_rev (void)
|
|
{
|
|
unsigned char part, vers, cfg;
|
|
|
|
part = in8 (PLD_PART_REG);
|
|
vers = in8 (PLD_VERS_REG);
|
|
cfg = in8 (PLD_BOARD_CFG_REG);
|
|
printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
|
|
16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
|
|
vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
|
|
}
|
|
|
|
extern void check_env(void);
|
|
|
|
|
|
int last_stage_init (void)
|
|
{
|
|
print_pip405_rev ();
|
|
isa_init ();
|
|
show_stdio_dev ();
|
|
check_env();
|
|
return 0;
|
|
}
|
|
|
|
/************************************************************************
|
|
* Print PIP405 Info
|
|
************************************************************************/
|
|
void print_pip405_info (void)
|
|
{
|
|
unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
|
|
compwr, nicvga, scsirst;
|
|
|
|
part = in8 (PLD_PART_REG);
|
|
vers = in8 (PLD_VERS_REG);
|
|
cfg = in8 (PLD_BOARD_CFG_REG);
|
|
ledu = in8 (PLD_LED_USER_REG);
|
|
sysman = in8 (PLD_SYS_MAN_REG);
|
|
flashcom = in8 (PLD_FLASH_COM_REG);
|
|
can = in8 (PLD_CAN_REG);
|
|
serpwr = in8 (PLD_SER_PWR_REG);
|
|
compwr = in8 (PLD_COM_PWR_REG);
|
|
nicvga = in8 (PLD_NIC_VGA_REG);
|
|
scsirst = in8 (PLD_SCSI_RST_REG);
|
|
printf ("PLD Part %d version %d\n",
|
|
part & 0xf, vers & 0xf);
|
|
printf ("PLD Part %d version %d\n",
|
|
(part >> 4) & 0xf, (vers >> 4) & 0xf);
|
|
printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
|
|
printf ("Population Options %d %d %d %d\n",
|
|
(cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
|
|
(cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
|
|
printf ("User LED0 %s User LED1 %s\n",
|
|
((ledu & 0x1) == 0x1) ? "on" : "off",
|
|
((ledu & 0x2) == 0x2) ? "on" : "off");
|
|
printf ("Additionally Options %d %d\n",
|
|
(ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
|
|
printf ("User Config Switch %d %d %d %d\n",
|
|
(ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
|
|
(ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
|
|
switch (sysman & 0x3) {
|
|
case 0:
|
|
printf ("PCI Clocks are running\n");
|
|
break;
|
|
case 1:
|
|
printf ("PCI Clocks are stopped in POS State\n");
|
|
break;
|
|
case 2:
|
|
printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
|
|
break;
|
|
case 3:
|
|
printf ("PCI Clocks are stopped\n");
|
|
break;
|
|
}
|
|
switch ((sysman >> 2) & 0x3) {
|
|
case 0:
|
|
printf ("Main Clocks are running\n");
|
|
break;
|
|
case 1:
|
|
printf ("Main Clocks are stopped in POS State\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("PCI Clocks are stopped\n");
|
|
break;
|
|
}
|
|
printf ("INIT asserts %sINT2# (SMI)\n",
|
|
((sysman & 0x10) == 0x10) ? "" : "not ");
|
|
printf ("INIT asserts %sINT1# (NMI)\n",
|
|
((sysman & 0x20) == 0x20) ? "" : "not ");
|
|
printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
|
|
printf ("SER1 is routed to %s\n",
|
|
((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
|
|
printf ("COM2 is routed to %s\n",
|
|
((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
|
|
printf ("RS485 is configured as %s duplex\n",
|
|
((flashcom & 0x4) == 0x4) ? "full" : "half");
|
|
printf ("RS485 is connected to %s\n",
|
|
((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
|
|
printf ("SER1 uses handshakes %s\n",
|
|
((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
|
|
printf ("Bootflash is %swriteprotected\n",
|
|
((flashcom & 0x20) == 0x20) ? "not " : "");
|
|
printf ("Bootflash VPP is %s\n",
|
|
((flashcom & 0x40) == 0x40) ? "on" : "off");
|
|
printf ("Bootsector is %swriteprotected\n",
|
|
((flashcom & 0x80) == 0x80) ? "not " : "");
|
|
switch ((can) & 0x3) {
|
|
case 0:
|
|
printf ("CAN Controller is on address 0x1000..0x10FF\n");
|
|
break;
|
|
case 1:
|
|
printf ("CAN Controller is on address 0x8000..0x80FF\n");
|
|
break;
|
|
case 2:
|
|
printf ("CAN Controller is on address 0xE000..0xE0FF\n");
|
|
break;
|
|
case 3:
|
|
printf ("CAN Controller is disabled\n");
|
|
break;
|
|
}
|
|
switch ((can >> 2) & 0x3) {
|
|
case 0:
|
|
printf ("CAN Controller Reset is ISA Reset\n");
|
|
break;
|
|
case 1:
|
|
printf ("CAN Controller Reset is ISA Reset and POS State\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("CAN Controller is in reset\n");
|
|
break;
|
|
}
|
|
if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
|
|
printf ("CAN Interrupt is disabled\n");
|
|
else
|
|
printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
|
|
switch (serpwr & 0x3) {
|
|
case 0:
|
|
printf ("SER0 Drivers are enabled\n");
|
|
break;
|
|
case 1:
|
|
printf ("SER0 Drivers are disabled in the POS state\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("SER0 Drivers are disabled\n");
|
|
break;
|
|
}
|
|
switch ((serpwr >> 2) & 0x3) {
|
|
case 0:
|
|
printf ("SER1 Drivers are enabled\n");
|
|
break;
|
|
case 1:
|
|
printf ("SER1 Drivers are disabled in the POS state\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("SER1 Drivers are disabled\n");
|
|
break;
|
|
}
|
|
switch (compwr & 0x3) {
|
|
case 0:
|
|
printf ("COM1 Drivers are enabled\n");
|
|
break;
|
|
case 1:
|
|
printf ("COM1 Drivers are disabled in the POS state\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("COM1 Drivers are disabled\n");
|
|
break;
|
|
}
|
|
switch ((compwr >> 2) & 0x3) {
|
|
case 0:
|
|
printf ("COM2 Drivers are enabled\n");
|
|
break;
|
|
case 1:
|
|
printf ("COM2 Drivers are disabled in the POS state\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("COM2 Drivers are disabled\n");
|
|
break;
|
|
}
|
|
switch ((nicvga) & 0x3) {
|
|
case 0:
|
|
printf ("PHY is running\n");
|
|
break;
|
|
case 1:
|
|
printf ("PHY is in Power save mode in POS state\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("PHY is in Power save mode\n");
|
|
break;
|
|
}
|
|
switch ((nicvga >> 2) & 0x3) {
|
|
case 0:
|
|
printf ("VGA is running\n");
|
|
break;
|
|
case 1:
|
|
printf ("VGA is in Power save mode in POS state\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("VGA is in Power save mode\n");
|
|
break;
|
|
}
|
|
printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
|
|
printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
|
|
printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
|
|
(nicvga >> 7) & 0x1);
|
|
switch ((scsirst) & 0x3) {
|
|
case 0:
|
|
printf ("SCSI Controller is running\n");
|
|
break;
|
|
case 1:
|
|
printf ("SCSI Controller is in Power save mode in POS state\n");
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
printf ("SCSI Controller is in Power save mode\n");
|
|
break;
|
|
}
|
|
printf ("SCSI termination is %s\n",
|
|
((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
|
|
printf ("SCSI Controller is %sreseted\n",
|
|
((scsirst & 0x10) == 0x10) ? "" : "not ");
|
|
printf ("IDE disks are %sreseted\n",
|
|
((scsirst & 0x20) == 0x20) ? "" : "not ");
|
|
printf ("ISA Bus is %sreseted\n",
|
|
((scsirst & 0x40) == 0x40) ? "" : "not ");
|
|
printf ("Super IO is %sreseted\n",
|
|
((scsirst & 0x80) == 0x80) ? "" : "not ");
|
|
}
|
|
|
|
void user_led0 (unsigned char on)
|
|
{
|
|
if (on == TRUE)
|
|
out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
|
|
else
|
|
out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
|
|
}
|
|
|
|
void user_led1 (unsigned char on)
|
|
{
|
|
if (on == TRUE)
|
|
out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
|
|
else
|
|
out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
|
|
}
|
|
|
|
void ide_set_reset (int idereset)
|
|
{
|
|
/* if reset = 1 IDE reset will be asserted */
|
|
unsigned char resreg;
|
|
|
|
resreg = in8 (PLD_SCSI_RST_REG);
|
|
if (idereset == 1)
|
|
resreg |= 0x20;
|
|
else {
|
|
udelay(10000);
|
|
resreg &= 0xdf;
|
|
}
|
|
out8 (PLD_SCSI_RST_REG, resreg);
|
|
}
|
|
|
|
|
|
|