upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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190 lines
5.1 KiB
190 lines
5.1 KiB
/*
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* Copyright 2004,2009 Freescale Semiconductor, Inc.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* cpu_init.c - low level cpu init
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*/
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#include <config.h>
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#include <common.h>
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#include <mpc86xx.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include <asm/mp.h>
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void setup_bats(void);
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map
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* initialize a bunch of registers
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*/
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void cpu_init_f(void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_lbc_t *memctl = &immap->im_lbc;
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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#ifdef CONFIG_FSL_LAW
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init_laws();
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#endif
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setup_bats();
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/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
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* addresses - these have to be modified later when FLASH size
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* has been determined
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*/
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#if defined(CONFIG_SYS_OR0_REMAP)
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memctl->or0 = CONFIG_SYS_OR0_REMAP;
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#endif
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#if defined(CONFIG_SYS_OR1_REMAP)
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memctl->or1 = CONFIG_SYS_OR1_REMAP;
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#endif
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/* now restrict to preliminary range */
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#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
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memctl->br0 = CONFIG_SYS_BR0_PRELIM;
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memctl->or0 = CONFIG_SYS_OR0_PRELIM;
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#endif
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#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
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memctl->or1 = CONFIG_SYS_OR1_PRELIM;
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memctl->br1 = CONFIG_SYS_BR1_PRELIM;
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#endif
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#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
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memctl->or2 = CONFIG_SYS_OR2_PRELIM;
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memctl->br2 = CONFIG_SYS_BR2_PRELIM;
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#endif
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#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
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memctl->or3 = CONFIG_SYS_OR3_PRELIM;
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memctl->br3 = CONFIG_SYS_BR3_PRELIM;
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#endif
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#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
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memctl->or4 = CONFIG_SYS_OR4_PRELIM;
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memctl->br4 = CONFIG_SYS_BR4_PRELIM;
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#endif
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#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
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memctl->or5 = CONFIG_SYS_OR5_PRELIM;
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memctl->br5 = CONFIG_SYS_BR5_PRELIM;
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#endif
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#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
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memctl->or6 = CONFIG_SYS_OR6_PRELIM;
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memctl->br6 = CONFIG_SYS_BR6_PRELIM;
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#endif
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#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
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memctl->or7 = CONFIG_SYS_OR7_PRELIM;
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memctl->br7 = CONFIG_SYS_BR7_PRELIM;
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#endif
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#if defined(CONFIG_FSL_DMA)
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dma_init();
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#endif
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/* enable the timebase bit in HID0 */
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set_hid0(get_hid0() | 0x4000000);
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/* enable EMCP, SYNCBE | ABE bits in HID1 */
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set_hid1(get_hid1() | 0x80000C00);
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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#if defined(CONFIG_MP)
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setup_mp();
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#endif
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return 0;
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}
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/* Set up BAT registers */
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void setup_bats(void)
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{
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#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L)
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write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
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#endif
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#if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
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write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
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#endif
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write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
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write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
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write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
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write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L);
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write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L);
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write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L);
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write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L);
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write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L);
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write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L);
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write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L);
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write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
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write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
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write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L);
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write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L);
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return;
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}
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#ifdef CONFIG_ADDR_MAP
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/* Initialize address mapping array */
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void init_addr_map(void)
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{
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int i;
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ppc_bat_t bat = DBAT0;
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phys_size_t size;
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unsigned long upper, lower;
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for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
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if (read_bat(bat, &upper, &lower) != -1) {
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if (!BATU_VALID(upper))
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size = 0;
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else
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size = BATU_SIZE(upper);
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addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
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size, i);
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}
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#ifdef CONFIG_HIGH_BATS
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/* High bats are not contiguous with low BAT numbers */
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if (bat == DBAT3)
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bat = DBAT4 - 1;
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#endif
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}
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}
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#endif
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