upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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412 lines
9.2 KiB
412 lines
9.2 KiB
/*
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* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct cpu_type cpu_type_list [] = {
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CPU_TYPE_ENTRY(8533, 8533),
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CPU_TYPE_ENTRY(8533, 8533_E),
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CPU_TYPE_ENTRY(8536, 8536),
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CPU_TYPE_ENTRY(8536, 8536_E),
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CPU_TYPE_ENTRY(8540, 8540),
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CPU_TYPE_ENTRY(8541, 8541),
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CPU_TYPE_ENTRY(8541, 8541_E),
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CPU_TYPE_ENTRY(8543, 8543),
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CPU_TYPE_ENTRY(8543, 8543_E),
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CPU_TYPE_ENTRY(8544, 8544),
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CPU_TYPE_ENTRY(8544, 8544_E),
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CPU_TYPE_ENTRY(8545, 8545),
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CPU_TYPE_ENTRY(8545, 8545_E),
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CPU_TYPE_ENTRY(8547, 8547_E),
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CPU_TYPE_ENTRY(8548, 8548),
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CPU_TYPE_ENTRY(8548, 8548_E),
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CPU_TYPE_ENTRY(8555, 8555),
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CPU_TYPE_ENTRY(8555, 8555_E),
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CPU_TYPE_ENTRY(8560, 8560),
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CPU_TYPE_ENTRY(8567, 8567),
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CPU_TYPE_ENTRY(8567, 8567_E),
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CPU_TYPE_ENTRY(8568, 8568),
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CPU_TYPE_ENTRY(8568, 8568_E),
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CPU_TYPE_ENTRY(8572, 8572),
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CPU_TYPE_ENTRY(8572, 8572_E),
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};
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struct cpu_type *identify_cpu(u32 ver)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if (cpu_type_list[i].soc_ver == ver)
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return &cpu_type_list[i];
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return NULL;
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}
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int checkcpu (void)
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{
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sys_info_t sysinfo;
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uint lcrr; /* local bus clock ratio register */
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uint clkdiv; /* clock divider portion of lcrr */
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uint pvr, svr;
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uint fam;
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uint ver;
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uint major, minor;
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struct cpu_type *cpu;
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char buf1[32], buf2[32];
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#ifdef CONFIG_DDR_CLK_FREQ
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
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>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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#else
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u32 ddr_ratio = 0;
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#endif
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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major = SVR_MAJ(svr);
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#ifdef CONFIG_MPC8536
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major &= 0x7; /* the msb of this nibble is a mfg code */
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#endif
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minor = SVR_MIN(svr);
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#if (CONFIG_NUM_CPUS > 1)
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volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
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printf("CPU%d: ", pic->whoami);
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#else
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puts("CPU: ");
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#endif
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cpu = identify_cpu(ver);
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if (cpu) {
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puts(cpu->name);
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if (IS_E_PROCESSOR(svr))
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puts("E");
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} else {
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puts("Unknown");
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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pvr = get_pvr();
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fam = PVR_FAM(pvr);
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ver = PVR_VER(pvr);
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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printf("Core: ");
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switch (fam) {
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case PVR_FAM(PVR_85xx):
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puts("E500");
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break;
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default:
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puts("Unknown");
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break;
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}
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if (PVR_MEM(pvr) == 0x03)
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puts("MC");
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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get_sys_info(&sysinfo);
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puts("Clock Configuration:\n");
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printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
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printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
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switch (ddr_ratio) {
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case 0x0:
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printf(" DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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break;
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case 0x7:
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printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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break;
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default:
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printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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break;
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}
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#if defined(CONFIG_SYS_LBC_LCRR)
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lcrr = CONFIG_SYS_LBC_LCRR;
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#else
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{
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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lcrr = lbc->lcrr;
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}
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#endif
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clkdiv = lcrr & 0x0f;
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if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
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#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
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defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
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/*
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* Yes, the entire PQ38 family use the same
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* bit-representation for twice the clock divider values.
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*/
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clkdiv *= 2;
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#endif
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printf("LBC:%-4s MHz\n",
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strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
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} else {
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printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
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}
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#ifdef CONFIG_CPM2
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printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
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#endif
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puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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{
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uint pvr;
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uint ver;
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unsigned long val, msr;
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pvr = get_pvr();
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ver = PVR_VER(pvr);
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if (ver & 1){
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/* e500 v2 core has reset control register */
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volatile unsigned int * rstcr;
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rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
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*rstcr = 0x2; /* HRESET_REQ */
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udelay(100);
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}
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/*
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* Fallthrough if the code above failed
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* Initiate hard reset in debug control register DBCR0
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* Make sure MSR[DE] = 1
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*/
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msr = mfmsr ();
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msr |= MSR_DE;
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mtmsr (msr);
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val = mfspr(DBCR0);
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val |= 0x70000000;
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mtspr(DBCR0,val);
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return 1;
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}
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/*
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* Get timebase clock frequency
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*/
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unsigned long get_tbclk (void)
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{
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return (gd->bus_clk + 4UL)/8UL;
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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int re_enable = disable_interrupts();
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reset_85xx_watchdog();
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if (re_enable) enable_interrupts();
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}
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void
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reset_85xx_watchdog(void)
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{
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/*
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* Clear TSR(WIS) bit by writing 1
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*/
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unsigned long val;
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val = mfspr(SPRN_TSR);
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val |= TSR_WIS;
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mtspr(SPRN_TSR, val);
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}
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_DDR_ECC)
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void dma_init(void) {
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volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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dma->satr0 = 0x02c40000;
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dma->datr0 = 0x02c40000;
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dma->sr0 = 0xfffffff; /* clear any errors */
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asm("sync; isync; msync");
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return;
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}
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uint dma_check(void) {
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volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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volatile uint status = dma->sr0;
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/* While the channel is busy, spin */
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while((status & 4) == 4) {
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status = dma->sr0;
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}
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/* clear MR0[CS] channel start bit */
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dma->mr0 &= 0x00000001;
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asm("sync;isync;msync");
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if (status != 0) {
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printf ("DMA Error: status = %x\n", status);
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}
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return status;
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}
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int dma_xfer(void *dest, uint count, void *src) {
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volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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dma->dar0 = (uint) dest;
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dma->sar0 = (uint) src;
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dma->bcr0 = count;
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dma->mr0 = 0xf000004;
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asm("sync;isync;msync");
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dma->mr0 = 0xf000005;
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asm("sync;isync;msync");
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return dma_check();
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}
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#endif
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/*
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* Configures a UPM. The function requires the respective MxMR to be set
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* before calling this function. "size" is the number or entries, not a sizeof.
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*/
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void upmconfig (uint upm, uint * table, uint size)
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{
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int i, mdr, mad, old_mad = 0;
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volatile u32 *mxmr;
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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volatile u32 *brp,*orp;
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volatile u8* dummy = NULL;
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int upmmask;
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switch (upm) {
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case UPMA:
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mxmr = &lbc->mamr;
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upmmask = BR_MS_UPMA;
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break;
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case UPMB:
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mxmr = &lbc->mbmr;
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upmmask = BR_MS_UPMB;
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break;
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case UPMC:
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mxmr = &lbc->mcmr;
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upmmask = BR_MS_UPMC;
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break;
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default:
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printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
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hang();
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}
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/* Find the address for the dummy write transaction */
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for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
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i++, brp += 2, orp += 2) {
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/* Look for a valid BR with selected UPM */
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if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
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dummy = (volatile u8*)(in_be32(brp) & BR_BA);
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break;
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}
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}
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if (i == 8) {
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printf("Error: %s() could not find matching BR\n", __FUNCTION__);
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hang();
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}
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for (i = 0; i < size; i++) {
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/* 1 */
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out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
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/* 2 */
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out_be32(&lbc->mdr, table[i]);
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/* 3 */
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mdr = in_be32(&lbc->mdr);
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/* 4 */
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*(volatile u8 *)dummy = 0;
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/* 5 */
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do {
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mad = in_be32(mxmr) & MxMR_MAD_MSK;
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} while (mad <= old_mad && !(!mad && i == (size-1)));
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old_mad = mad;
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}
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out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
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}
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_ETHER_ON_FCC)
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fec_initialize(bis);
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#endif
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#if defined(CONFIG_UEC_ETH1)
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uec_initialize(0);
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#endif
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#if defined(CONFIG_UEC_ETH2)
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uec_initialize(1);
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#endif
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#if defined(CONFIG_UEC_ETH3)
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uec_initialize(2);
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#endif
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#if defined(CONFIG_UEC_ETH4)
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uec_initialize(3);
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#endif
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#if defined(CONFIG_UEC_ETH5)
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uec_initialize(4);
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#endif
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#if defined(CONFIG_UEC_ETH6)
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uec_initialize(5);
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#endif
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
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tsec_standard_init(bis);
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#endif
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return 0;
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}
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