upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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379 lines
10 KiB
379 lines
10 KiB
/*
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Board specific routines for the MBX
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*
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* - initialisation
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* - interface to VPD data (mac address, clock speeds)
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* - memory controller
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* - serial io initialisation
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* - ethernet io initialisation
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*
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* -----------------------------------------------------------------
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <commproc.h>
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#include <mpc8xx.h>
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#include "dimm.h"
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#include "vpd.h"
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#include "csr.h"
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/* ------------------------------------------------------------------------- */
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static const uint sdram_table_40[] = {
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/* DRAM - single read. (offset 0 in upm RAM)
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*/
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0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
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0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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/* DRAM - burst read. (offset 8 in upm RAM)
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*/
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0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
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0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
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0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
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0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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/* DRAM - single write. (offset 18 in upm RAM)
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*/
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0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804,
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0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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/* DRAM - burst write. (offset 20 in upm RAM)
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*/
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0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
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0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
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0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
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0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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/* refresh (offset 30 in upm RAM)
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*/
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0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
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0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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/* exception. (offset 3c in upm RAM)
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*/
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0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
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};
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static const uint sdram_table_50[] = {
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/* DRAM - single read. (offset 0 in upm RAM)
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*/
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0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
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0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
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/* DRAM - burst read. (offset 8 in upm RAM)
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*/
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0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04,
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/* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */
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0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08,
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0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04,
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/* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */
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0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005,
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/* DRAM - single write. (offset 18 in upm RAM)
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*/
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0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
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0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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/* DRAM - burst write. (offset 20 in upm RAM)
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*/
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0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
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0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
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0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
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0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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/* refresh (offset 30 in upm RAM)
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*/
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0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
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0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
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0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
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/* exception. (offset 3c in upm RAM)
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*/
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0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
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};
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/* ------------------------------------------------------------------------- */
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static unsigned int get_reffreq(void);
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static unsigned int board_get_cpufreq(void);
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void mbx_init (void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immr->im_memctl;
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ulong speed, refclock, plprcr, sccr;
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ulong br0_32 = memctl->memc_br0 & 0x400;
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/* real-time clock status and control register */
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immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
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immr->im_sit.sit_rtcsc = 0x00C3;
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/* SIEL and SIMASK Registers (see MBX PRG 2-3) */
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immr->im_siu_conf.sc_simask = 0x00000000;
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immr->im_siu_conf.sc_siel = 0xAAAA0000;
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immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;
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/*
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* Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus:
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* 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h)
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* 2. RAM Specs (see dimm.h)
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* 2. DIMM Specs (see dimm.h)
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*/
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vpd_init ();
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/* system clock and reset control register */
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immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
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sccr = immr->im_clkrst.car_sccr;
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sccr &= SCCR_MASK;
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sccr |= CFG_SCCR;
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immr->im_clkrst.car_sccr = sccr;
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speed = board_get_cpufreq ();
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refclock = get_reffreq ();
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#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
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plprcr = CFG_PLPRCR;
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#else
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plprcr = immr->im_clkrst.car_plprcr;
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plprcr &= PLPRCR_MF_MSK; /* isolate MF field */
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plprcr |= CFG_PLPRCR; /* reset control bits */
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#endif
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#ifdef CFG_USE_OSCCLK /* See doc/README.MBX ! */
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plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
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#endif
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immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
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immr->im_clkrst.car_plprcr = plprcr;
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/*
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* preliminary setup of memory controller:
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* - map Flash, otherwise configuration/status
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* registers won't be accessible when read
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* by board_init_f.
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* - map NVRAM and configuation/status registers.
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* - map pci registers.
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* - DON'T map ram yet, this is done in initdram().
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*/
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switch (speed / 1000000) {
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case 40:
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memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
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memctl->memc_or0 = 0xFF800930;
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memctl->memc_or4 = CFG_NVRAM_OR | 0x920;
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memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
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break;
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case 50:
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memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
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memctl->memc_or0 = 0xFF800940;
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memctl->memc_or4 = CFG_NVRAM_OR | 0x930;
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memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
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break;
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default:
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hang ();
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break;
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}
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#ifdef CONFIG_USE_PCI
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memctl->memc_or5 = CFG_PCIMEM_OR;
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memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001;
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memctl->memc_or6 = CFG_PCIBRIDGE_OR;
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memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001;
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#endif
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/*
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* FIXME: I do not understand why I have to call this to
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* initialise the control register here before booting from
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* the PCMCIA card but if I do not the Linux kernel falls
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* over in a big heap. If you can answer this question I
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* would like to know about it.
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*/
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board_ether_init();
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}
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void board_serial_init (void)
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{
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MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS);
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}
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void board_ether_init (void)
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{
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MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN);
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MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS;
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}
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static unsigned int board_get_cpufreq (void)
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{
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#ifndef CONFIG_8xx_GCLK_FREQ
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vpd_packet_t *packet;
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packet = vpd_find_packet (VPD_PID_ICS);
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return *((ulong *) packet->data);
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#else
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return((unsigned int)CONFIG_8xx_GCLK_FREQ );
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#endif /* CONFIG_8xx_GCLK_FREQ */
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}
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static unsigned int get_reffreq (void)
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{
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vpd_packet_t *packet;
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packet = vpd_find_packet (VPD_PID_RCS);
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return *((ulong *) packet->data);
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}
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void board_get_enetaddr (uchar * addr)
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{
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int i;
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vpd_packet_t *packet;
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packet = vpd_find_packet (VPD_PID_EA);
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for (i = 0; i < 6; i++)
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addr[i] = packet->data[i];
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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vpd_packet_t *packet;
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int i;
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const char *const fmt =
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"\n *** Warning: Low Battery Status - %s Battery ***";
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puts ("Board: ");
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packet = vpd_find_packet (VPD_PID_PID);
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for (i = 0; i < packet->size; i++) {
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serial_putc (packet->data[i]);
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}
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packet = vpd_find_packet (VPD_PID_MT);
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for (i = 0; i < packet->size; i++) {
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serial_putc (packet->data[i]);
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}
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serial_putc ('(');
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packet = vpd_find_packet (VPD_PID_FAN);
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for (i = 0; i < packet->size; i++) {
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serial_putc (packet->data[i]);
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}
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serial_putc (')');
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if (!(MBX_CSR2 & SR2_BATGD))
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printf (fmt, "On-Board");
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if (!(MBX_CSR2 & SR2_NVBATGD))
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printf (fmt, "NVRAM");
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serial_putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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static ulong get_ramsize (dimm_t * dimm)
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{
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ulong size = 0;
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if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3
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|| dimm->fmt == 4) {
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size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks *
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((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8);
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}
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return size;
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}
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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unsigned long ram_sz = 0;
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unsigned long dimm_sz = 0;
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dimm_t vpd_dimm, vpd_dram;
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unsigned int speed = board_get_cpufreq () / 1000000;
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if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) {
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dimm_sz = get_ramsize (&vpd_dimm);
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}
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if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) {
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ram_sz = get_ramsize (&vpd_dram);
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}
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/*
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* Only initialize memory controller when running from FLASH.
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* When running from RAM, don't touch it.
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*/
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if ((ulong) initdram & 0xff000000) {
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ulong dimm_bank;
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ulong br0_32 = memctl->memc_br0 & 0x400;
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switch (speed) {
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case 40:
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upmconfig (UPMA, (uint *) sdram_table_40,
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sizeof (sdram_table_40) / sizeof (uint));
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memctl->memc_mptpr = 0x0200;
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memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
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memctl->memc_or7 = 0xff800930;
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memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
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break;
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case 50:
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upmconfig (UPMA, (uint *) sdram_table_50,
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sizeof (sdram_table_50) / sizeof (uint));
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memctl->memc_mptpr = 0x0200;
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memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
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memctl->memc_or7 = 0xff800940;
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memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
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break;
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default:
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hang ();
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break;
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}
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/* now map ram and dimm, largest one first */
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dimm_bank = dimm_sz / 2;
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if (!dimm_sz) {
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memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
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memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
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memctl->memc_br2 = 0;
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memctl->memc_br3 = 0;
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} else if (ram_sz > dimm_bank) {
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memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
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memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
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memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
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memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81;
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memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
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memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) \
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| 0x81;
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} else {
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memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
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memctl->memc_br2 = CFG_SDRAM_BASE | 0x81;
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memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
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memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81;
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memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
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memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81;
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}
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}
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return ram_sz + dimm_sz;
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}
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