upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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466 lines
16 KiB
466 lines
16 KiB
/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
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#define CONFIG_IP860 1 /* ...on a IP860 board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
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"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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# define CFG_I2C_SPEED 50000
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# define CFG_I2C_SLAVE 0xFE
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# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
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# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SNTP
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF1000000 /* Non-standard value!! */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x10000000
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#ifdef DEBUG
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#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
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#else
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#if 0 /* need more space for I2C tests */
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#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (256 << 10)
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#endif
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#undef CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_ENV_IS_IN_NVRAM
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#undef CONFIG_ENV_IS_IN_NVRAM
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#undef DEBUG_I2C
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#define CONFIG_ENV_IS_IN_EEPROM
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#ifdef CONFIG_ENV_IS_IN_NVRAM
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#define CONFIG_ENV_ADDR 0x20000000 /* use SRAM */
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#define CONFIG_ENV_SIZE (16<<10) /* use 16 kB */
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#endif /* CONFIG_ENV_IS_IN_NVRAM */
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
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#define CONFIG_ENV_SIZE 1536 /* Use remaining space */
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#endif /* CONFIG_ENV_IS_IN_EEPROM */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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* +0x0004
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* +0x0000 => 0x80600800
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*/
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#define CFG_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \
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SIUMCR_DBGC11 | SIUMCR_MLRC10)
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/*-----------------------------------------------------------------------
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* Clock Setting - get clock frequency from Board Revision Register
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*-----------------------------------------------------------------------
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*/
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#ifndef __ASSEMBLY__
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extern unsigned long ip860_get_clk_freq (void);
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#endif
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#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq()
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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* +0x0200 => 0x00C2
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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* +0x0240 => 0x0082
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit, set PLL multiplication factor !
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*/
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/* +0x0286 => was: 0x0000D000 */
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#define CFG_PLPRCR \
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( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
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/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
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PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
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)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \
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SCCR_RTDIV | SCCR_RTSEL | \
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/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
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SCCR_EBDF00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000 | \
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SCCR_DFNH000)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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/* +0x0220 => 0x00C3 */
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration Register 19-4
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*-----------------------------------------------------------------------
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*/
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/* +0x09C4 => TIMEP=1 */
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#define CFG_RCCR 0x0100
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/*-----------------------------------------------------------------------
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* RMDS - RISC Microcode Development Support Control Register
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*-----------------------------------------------------------------------
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*/
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#define CFG_RMDS 0
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/*-----------------------------------------------------------------------
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* DER - Debug Event Register
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_DER 0
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/*
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* Init Memory Controller:
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*/
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/*
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* MAMR settings for SDRAM - 16-14
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* => 0xC3804114
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*/
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/* periodic timer for refresh */
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#define CFG_MAMR_PTA 0xC3
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#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/*
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* BR1 and OR1 (FLASH)
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*/
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#define FLASH_BASE 0x10000000 /* FLASH bank #0 */
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/* used to re-map FLASH
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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/* allow for max 8 MB of Flash */
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#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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/* 16 bit, bank valid */
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#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
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#define CFG_OR1_PRELIM CFG_OR0_PRELIM
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#define CFG_BR1_PRELIM CFG_BR0_PRELIM
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/*
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* BR2/OR2 - SDRAM
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*/
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#define SDRAM_BASE 0x00000000 /* SDRAM bank */
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#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
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#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
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#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
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#define CFG_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
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/*
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* BR3/OR3 - SRAM (16 bit)
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*/
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#define SRAM_BASE 0x20000000
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#define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
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#define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
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#define SRAM_SIZE (1 + (~(CFG_OR3 & BR_BA_MSK)))
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#define CFG_OR3_PRELIM CFG_OR3 /* Make sure to map early */
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#define CFG_BR3_PRELIM CFG_BR3 /* in case it's used for ENV */
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/*
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* BR4/OR4 - Board Control & Status (8 bit)
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*/
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#define BCSR_BASE 0xFC000000
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#define CFG_OR4 0xFFFF0120 /* BI (internal) */
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#define CFG_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
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/*
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* BR5/OR5 - IP Slot A/B (16 bit)
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*/
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#define IP_SLOT_BASE 0x40000000
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#define CFG_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
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#define CFG_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
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/*
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* BR6/OR6 - VME STD (16 bit)
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*/
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#define VME_STD_BASE 0xFE000000
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#define CFG_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
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#define CFG_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
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/*
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* BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
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*/
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#define VME_SHORT_BASE 0xFF000000
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#define CFG_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
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#define CFG_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
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/*-----------------------------------------------------------------------
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* Board Control and Status Region:
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*-----------------------------------------------------------------------
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*/
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#ifndef __ASSEMBLY__
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typedef struct ip860_bcsr_s {
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unsigned char shmem_addr; /* +00 shared memory address register */
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unsigned char reserved0;
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unsigned char mbox_addr; /* +02 mailbox address register */
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unsigned char reserved1;
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unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
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unsigned char reserved2;
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unsigned char vme_int_pend; /* +06 VME interrupt pending register */
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unsigned char reserved3;
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unsigned char bd_int_mask; /* +08 board interrupt mask register */
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unsigned char reserved4;
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unsigned char bd_int_pend; /* +0A board interrupt pending register */
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unsigned char reserved5;
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unsigned char bd_ctrl; /* +0C board control register */
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unsigned char reserved6;
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unsigned char bd_status; /* +0E board status register */
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unsigned char reserved7;
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unsigned char vme_irq; /* +10 VME interrupt request register */
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unsigned char reserved8;
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unsigned char vme_ivec; /* +12 VME interrupt vector register */
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unsigned char reserved9;
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unsigned char cli_mbox; /* +14 clear mailbox irq */
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unsigned char reservedA;
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unsigned char rtc; /* +16 RTC control register */
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unsigned char reservedB;
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unsigned char mbox_data; /* +18 mailbox read/write register */
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unsigned char reservedC;
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unsigned char wd_trigger; /* +1A Watchdog trigger register */
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unsigned char reservedD;
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unsigned char rmw_req; /* +1C RMW request register */
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unsigned char reservedE;
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unsigned char bd_rev; /* +1E Board Revision register */
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} ip860_bcsr_t;
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#endif /* __ASSEMBLY__ */
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/*-----------------------------------------------------------------------
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* Board Control Register: bd_ctrl (Offset 0x0C)
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*-----------------------------------------------------------------------
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*/
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#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
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#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
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#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
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#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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