upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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415 lines
12 KiB
415 lines
12 KiB
/*
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* (C) Copyright 2004
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* Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
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*
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* Support for the Elmeg VoVPN Gateway Module
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* define cpu used */
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#define CONFIG_MPC8272 1
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/* define busmode: 8260 */
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#undef CONFIG_BUSMODE_60x
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/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
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#ifdef CONFIG_CLKIN_66MHz
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#define CONFIG_8260_CLKIN 66666666 /* in Hz */
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#else
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#define CONFIG_8260_CLKIN 100000000 /* in Hz */
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#endif
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/* call board_early_init_f */
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#define CONFIG_BOARD_EARLY_INIT_F 1
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/* have misc_init_r() function */
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#define CONFIG_MISC_INIT_R 1
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/* have reset_phy_r() function */
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#define CONFIG_RESET_PHY_R 1
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/* have special reset function */
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#define CONFIG_HAVE_OWN_RESET 1
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/* allow serial and ethaddr to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/* watchdog disabled */
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#undef CONFIG_WATCHDOG
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/* include support for bzip2 compressed images */
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#undef CONFIG_BZIP2
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/* status led */
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#undef CONFIG_STATUS_LED /* XXX jse */
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/* vendor parameter protection */
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#define CONFIG_ENV_OVERWRITE
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC
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#undef CONFIG_CONS_ON_SCC
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#undef CONFIG_CONS_NONE
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#define CONFIG_CONS_INDEX 1
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/* serial port default baudrate */
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#define CONFIG_BAUDRATE 115200
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/* echo on for serial download */
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#define CONFIG_LOADS_ECHO 1
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/* don't allow baudrate change */
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#undef CFG_LOADS_BAUD_CHANGE
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/* supported baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC
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#define CONFIG_ETHER_ON_FCC
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#undef CONFIG_ETHER_NONE
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#ifdef CONFIG_ETHER_ON_FCC
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/* which SCC/FCC channel for ethernet */
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#define CONFIG_ETHER_INDEX 1
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/* Marvell Switch SMI base addr */
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#define CFG_PHY_ADDR 0x10
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/* FCC1 RMII REFCLK is CLK10 */
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#define CFG_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
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#define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK)
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/* BDs and buffers on 60x bus */
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#define CFG_CPMFCR_RAMTYPE 0
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/* Local Protect, Full duplex, Flowcontrol, RMII */
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#define CFG_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\
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FCC_PSMR_FCE|FCC_PSMR_RMII)
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/* bit-bang MII PHY management */
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#define CONFIG_BITBANGMII
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#define MDIO_PORT 1 /* Port B */
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#define CFG_MDIO_PIN 0x00002000 /* PB18 */
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#define CFG_MDC_PIN 0x00001000 /* PB19 */
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#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
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#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
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#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
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else iop->pdat &= ~CFG_MDIO_PIN
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#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
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else iop->pdat &= ~CFG_MDC_PIN
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#define MIIDELAY udelay(1)
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_AUTOSCRIPT
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_CONSOLE
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_IMLS
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RUN
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/*
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* boot options & environment
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*/
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"clean_nv=erase fff20000 ffffffff\0" \
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"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
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"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
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"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
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"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
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"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
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"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
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"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
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"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
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"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
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"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
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"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
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"fstype=cramfs\0" \
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"rootpath=/root_fs\0" \
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"uboot=PPC/u-boot.bin\0" \
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"kernel=PPC/uImage\0" \
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"kernel_addr=ffe00000\0" \
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"fs=PPC/root_fs\0" \
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"console=ttyS0\0" \
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"netdev=eth0\0" \
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"rootdev=31:3\0" \
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"ethaddr=00:09:4f:01:02:03\0" \
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"ipaddr=10.0.0.201\0" \
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"netmask=255.255.255.0\0" \
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"serverip=10.0.0.136\0" \
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"gatewayip=10.0.0.10\0" \
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"hostname=bastard\0" \
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""
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/*
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* miscellaneous configurable options
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*/
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/* undef to save memory */
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#define CFG_LONGHELP
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/* monitor command prompt */
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#define CFG_PROMPT "=> "
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/* console i/o buffer size */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024
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#else
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#define CFG_CBSIZE 256
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#endif
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/* print buffer size */
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
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/* max number of command args */
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#define CFG_MAXARGS 16
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/* boot argument buffer size */
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#define CFG_BARGSIZE CFG_CBSIZE
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/* memtest works on */
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#define CFG_MEMTEST_START 0x00100000
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/* 1 ... 15 MB in DRAM */
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#define CFG_MEMTEST_END 0x00f00000
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/* full featured memtest */
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#define CFG_ALT_MEMTEST
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/* default load address */
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#define CFG_LOAD_ADDR 0x00100000
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/* decrementer freq: 1 ms ticks */
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#define CFG_HZ 1000
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/* configure flash */
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#define CFG_FLASH_BASE 0xff800000
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 64
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#define CFG_FLASH_SIZE 8
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#undef CFG_FLASH_16BIT
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#define CFG_FLASH_ERASE_TOUT 240000
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#define CFG_FLASH_WRITE_TOUT 500
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#define CFG_FLASH_LOCK_TOUT 500
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#define CFG_FLASH_UNLOCK_TOUT 10000
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#define CFG_FLASH_PROTECTION
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/* monitor in flash */
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#define CFG_MONITOR_OFFSET 0x00700000
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/* environment in flash */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00020000)
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#define CONFIG_ENV_SIZE 0x00020000
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#define CONFIG_ENV_SECT_SIZE 0x00020000
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/*
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* Initial memory map for linux
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20)
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/* hard reset configuration words */
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#ifdef CONFIG_CLKIN_66MHz
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#define CFG_HRCW_MASTER 0x04643050
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#else
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#error NO HRCW FOR 100MHZ SPECIFIED !!!
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#endif
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#define CFG_HRCW_SLAVE1 0x00000000
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#define CFG_HRCW_SLAVE2 0x00000000
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#define CFG_HRCW_SLAVE3 0x00000000
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#define CFG_HRCW_SLAVE4 0x00000000
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#define CFG_HRCW_SLAVE5 0x00000000
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#define CFG_HRCW_SLAVE6 0x00000000
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#define CFG_HRCW_SLAVE7 0x00000000
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/* internal memory mapped register */
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#define CFG_IMMR 0xF0000000
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/* definitions for initial stack pointer and data area (in DPRAM) */
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2000
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#define CFG_GBL_DATA_SIZE 128
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_SIZE (32*1024*1024)
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_FLASH (CFG_FLASH_BASE + CFG_MONITOR_OFFSET)
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#define CFG_MONITOR_LEN 0x00020000
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#define CFG_MALLOC_LEN 0x00020000
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/* boot flags */
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#define BOOTFLAG_COLD 0x01 /* normal power-on */
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#define BOOTFLAG_WARM 0x02 /* software reboot */
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/* cache configuration */
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#define CFG_CACHELINE_SIZE 32 /* for MPC8260 */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */
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#endif
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/*
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* HIDx - Hardware Implementation-dependent Registers
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|\
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HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
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#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
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#define CFG_HID2 0
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/* RMR - reset mode register - turn on checkstop reset enable */
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#define CFG_RMR RMR_CSRE
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/* BCR - bus configuration */
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#define CFG_BCR 0x00000000
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/* SIUMCR - siu module configuration */
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#define CFG_SIUMCR 0x4905c000
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/* SYPCR - system protection control */
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR 0xffffff87
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#else
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#define CFG_SYPCR 0xffffff83
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#endif
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/* TMCNTSC - time counter status and control */
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/* clear interrupts XXX jse */
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/*#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */
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#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\
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TMCNTSC_TCF|TMCNTSC_TCE)
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/* PISCR - periodic interrupt status and control */
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/* clear interrupts XXX jse */
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/*#define CFG_PISCR (PISCR_PS) */
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/* SCCR - system clock control */
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#define CFG_SCCR 0x000001a9
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/* RCCR - risc controller configuration */
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#define CFG_RCCR 0
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/*
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* MEMORY MAP
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* ----------
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* CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
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* CS1 - SDRAM 32MB/64Bit base=0x00000000
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* CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
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* CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
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* CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
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* CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
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* CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
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* x - IMMR 384KB base=0xf0000000
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*/
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/* XXX jse 100MHz TODO */
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#define CFG_BR0_PRELIM 0xff800801
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#define CFG_OR0_PRELIM 0xff801e44
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#define CFG_BR1_PRELIM 0x00000041
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#define CFG_OR1_PRELIM 0xfe002ec0
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#if 1
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#define CFG_BR2_PRELIM 0xf0101001
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#define CFG_OR2_PRELIM 0xfff00ef4
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#define CFG_BR3_PRELIM 0xf0201001
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#define CFG_OR3_PRELIM 0xfff00ef4
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#define CFG_BR4_PRELIM 0xf0301001
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#define CFG_OR4_PRELIM 0xfff00ef4
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#define CFG_BR5_PRELIM 0xf0401001
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#define CFG_OR5_PRELIM 0xfff00ef4
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#else
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#define CFG_BR2_PRELIM 0xf0101081
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#define CFG_OR2_PRELIM 0xfff00104
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#define CFG_BR3_PRELIM 0xf0201081
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#define CFG_OR3_PRELIM 0xfff00104
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#define CFG_BR4_PRELIM 0xf0301081
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#define CFG_OR4_PRELIM 0xfff00104
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#define CFG_BR5_PRELIM 0xf0401081
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#define CFG_OR5_PRELIM 0xfff00104
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#endif
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#define CFG_BR7_PRELIM 0xf0500881
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#define CFG_OR7_PRELIM 0xffff8104
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#define CFG_MPTPR 0x2700
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#define CFG_PSDMR 0x822a2452 /* optimal */
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/*#define CFG_PSDMR 0x822a48a3 */ /* relaxed */
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#define CFG_PSRT 0x1a
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/* "bad" address */
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#define CFG_RESET_ADDRESS 0x40000000
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#endif /* __CONFIG_H */
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